PA-7100LC
Low-cost PA-RISC microprocessor with on-die memory controller and MAX-1 SIMD.
The PA-7100LC, code-named Hummingbird (also known as the PCX-L), is a microprocessor from Hewlett-Packard that runs the PA-RISC 1.1 instruction set architecture. It was built as a budget-friendly chip for entry-level systems. The first machines using it hit the market in January 1994, running at 60 or 80 MHz, with a 100 MHz version arriving that June. This processor was the first PA-RISC chip to include the MAX-1 multimedia instructions, an early SIMD extension aimed at speeding up MPEG video decoding.
The PA-7100LC was based on the PA-7100, with key upgrades including better superscalar execution and an extra integer unit. It also added architectural features like the MAX-1 instructions, support for uncacheable memory pages, and bi-endian capability. The superscalar improvements came from that extra integer unit and tweaked control logic, allowing two integer instructions, two load-store operations, or a mix of one integer and one load or store to be issued in a single cycle—on top of the combinations the PA-7100 already handled.
Several circuit changes were made from the PA-7100LC’s design. Notably, the floating-point unit’s multiplier was shrunk by halving the tree of carry-save adders that summed partial products of the mantissa. This kept single-precision multiply latency at two cycles but bumped double-precision multiplies to three cycles. The trade-off was considered fine since the chip targeted mid-range multimedia workstations, where single-precision math is more common. To cut costs, a memory controller (supporting up to 2 GB) and an I/O controller were integrated directly on the die.
The cache layout differs from most HP-designed PA-RISC CPUs. Instead of large external instruction and data caches, the PA-7100LC uses a tiny 1 KB on-die instruction cache paired with a single large external unified cache (for both instructions and data) ranging from 8 KB to 2 MB.
The chip contains 900,000 transistors and measures 14.2 by 14.2 mm (201.64 mm²). It was made by HP using their 0.8 µm, three-level-metal CMOS26B process, and packaged in a 432-pin ceramic pin grid array.
The PA-7300LC, introduced in mid-1996, is a further evolution of the PA-7100LC. It served as a low-end to mid-range chip alongside the high-end PA-8000 in HP’s workstations and servers.
- Introduced
- January 1994 (60 and 80 MHz); June 1994 (100 MHz)
- Transistor count
- 900,000
- Die size
- 14.2 by 14.2 mm (201.64 mm²)
- Fabrication process
- HP 0.8 μm three-level metal CMOS26B
- Package
- 432-pin ceramic pin grid array
- Cache
- on-die 1 KB instruction cache; external unified cache 8 KB to 2 MB
Lore & Background
The PA-7100LC was based on the PA-7100, with major improvements including improved superscalar execution and an extra integer unit. Superscalar execution was enhanced by adding the extra integer unit and modifying control logic so that two integer instructions, two load–store unit operations, or an integer and a load or a store could be issued in one cycle, in addition to existing instruction combinations. Architectural improvements also included the MAX-1 multimedia instructions, uncacheable memory pages, and bi-endian support.
A number of modifications were made to circuits derived from the PA-7100LC. The floating-point unit multiplier was modified to take up less area by halving the tree of carry-save adders that summed the partial products of the mantissa. This left the latency of single precision multiplies unchanged at two cycles, but increased the latency of double-precision multiplies to three cycles. The performance loss was deemed acceptable as the PA-7100LC was designed for mid-range multimedia workstations where single-precision multiplies are more prevalent.
Integrated on-die to lower costs were a memory controller supporting up to 2 GB of memory and an I/O controller. The cache organization differed from most HP-designed PA-RISC CPUs: the large external instruction and data caches were replaced by an on-die instruction cache with a 1 KB capacity and a large external 8 KB to 2 MB cache, which was unified for both instructions and data.
Reader's Guide
The PA-7100LC represented a strategic move by Hewlett-Packard to offer a lower-cost microprocessor for low-end systems while retaining PA-RISC compatibility. Its integration of a memory controller and I/O controller on-die reduced system cost, and its introduction of the MAX-1 SIMD multimedia instructions marked an early effort to accelerate MPEG video decoding in software. The design trade-off in the floating-point unit—halving the carry-save adder tree to save area at the cost of slower double-precision multiplies—reflected a focus on the single-precision workloads common in multimedia workstations. The PA-7100LC's superscalar improvements, including an extra integer unit and enhanced instruction issue logic, built on the PA-7100 foundation. Its cache architecture, with a small on-die instruction cache and a larger unified external cache, was a departure from typical HP PA-RISC designs. The processor's 900,000 transistors and 0.8 μm CMOS26B process were typical for its era. The PA-7100LC directly led to the PA-7300LC, which integrated larger on-chip caches and further evolved the design for mid-range systems.
Did You Know?
- The PA-7100LC is also known by its code-name Hummingbird.
- It was the first PA-RISC microprocessor to implement the MAX-1 multimedia instructions.
- The floating-point unit multiplier's tree of carry-save adders was halved to reduce area, increasing double-precision multiply latency to three cycles.
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