Motorola 68060

Lore & Background

The 68060 shares most architectural features with the P5 Pentium, including a similar superscalar in-order dual instruction pipeline configuration and an instruction decoder that breaks down complex instructions into simpler ones before execution. These translated instructions are stored in a 16-entry FIFO buffer, with more complex 68000 instructions occupying multiple entries. A significant difference to the Pentium is that the 68060 FPU is not pipelined and is therefore up to three times slower in floating point applications, while integer multiplications and bit shifting instructions are significantly faster. The 68060 can execute simple instructions in the address generation unit (AGU) and supply the result two cycles before the ALU.

The 68060 was introduced at 50 MHz on Motorola's 0.6 μm manufacturing process, later shrunk to 0.42 μm with clock speeds raised to 66 MHz and 75 MHz. Some users managed to overclock rev6 68060 CPUs (mask 71E41J) up to 120 or 133 MHz. Motorola projected performance of around three-and-a-half times that of a 25 MHz 68040 at 50 MHz, described as 'about 77 MIPS', later adjusting to three times the performance for a 68060 running at twice the frequency of the 68040. Benchmarking of the 50 MHz 68060 in Amiga accelerator cards indicated Dhrystone 2.1 results of around 80,000 Dhrystones per second, broadly comparable to a Sun SPARCstation 10 workstation.

The 68060 saw use in late-model Amiga machines and accelerator cards, Atari ST clones and Falcon accelerator boards (CT60/CT63/CT60e, the latter created in 2015), and very late Alpha Microsystems multiuser computers. Apple Inc. had indicated commitment to the 68040 and its anticipated successor (the 68050) but by the arrival of the 68060 had already announced adoption of PowerPC. Motorola anticipated Apple might leave space for 68060-based products as 'a high performance hedge' against the RISC transition, but the Apple Workgroup Server range transitioned directly from 68040 to PowerPC processors.

Reader's Guide

The 68060 represents the culmination of the 68000 series for general-purpose computing, abandoned by Motorola in favor of the PowerPC architecture. Its design was heavily influenced by analysis of commercial compiled code to identify optimization opportunities. Against the Pentium, the 68060 could perform better on mixed code because its decoder could issue an FP instruction whenever the non-pipelined FPU could accept one, making optimization easier for programmers. However, with properly optimized and scheduled code, the Pentium's FPU could achieve double the clock-for-clock throughput. The 68060's legacy extends beyond desktop computing into embedded systems, where developments of its basic core continue under the names ColdFire and DragonBall, combined with peripheral interfaces to reduce complexity and power requirements. The processor also found use in telecommunications equipment such as Nortel Meridian 1 PBX systems and Wellfleet routers, as well as in television character generators from Chyron. The Q60 motherboard for the Sinclair QL demonstrated the architecture's longevity, running the same operating systems at over 100 times the speed of the original QL.

Did You Know?

• The 68060 design was led by Joe Circello.
• Motorola never produced a 68050, though it was planned at one point.
• Some users overclocked rev6 68060 CPUs up to 120 or 133 MHz.
• The 68060 is the last 68000 family processor from Motorola.

Superscalar Architecture and Microarchitectural Innovation

The 68060 represented a fundamental shift in how the 68k family approached instruction execution. As the sole member of the fourth generation, it abandoned the simpler pipeline designs of its predecessors in favor of a superscalar architecture capable of handling multiple instructions in parallel. Its ten-stage pipeline was the longest in the entire family, and a dual instruction pipeline allowed the processor to fetch and decode more than one instruction per cycle. Branch prediction was introduced to reduce the penalty of conditional jumps, while the address generation unit was engineered to deliver its results two full cycles before the arithmetic logic unit required them, effectively overlapping these two critical operations. The chip carried 8 KB of both instruction and data cache, double the capacity of the 68040. A dedicated unit completed integer multiplications in just two cycles without stalling the rest of the pipeline. Collectively, these design choices marked the most aggressive performance push Motorola ever made within the CISC 68k framework.

Culmination of a Four-Generation Evolution

The 68060 sat at the very top of a four-generation evolutionary ladder Motorola had been climbing since the original 68000. Each prior generation had layered on new capabilities: the 68020 delivered a fully 32-bit ALU, a three-stage pipeline, and a 256-byte instruction cache; the 68030 added split instruction and data caches of 256 bytes each plus an on-chip memory management unit; the 68040 expanded those caches to 4 KB, stretched the pipeline to six stages, and integrated a floating-point unit directly on the die. The 68060 inherited all of that groundwork and pushed further with its superscalar execution model. Motorola offered it in three tiers: the full-featured 68060, the 68EC060 which stripped out both the FPU and MMU for cost-sensitive designs, and the 68LC060 which omitted only the FPU. This tiered strategy echoed the approach used across every prior generation, yet the 68060's internal complexity made it the most ambitious chip the 68k line ever produced.

The Final Chapter and the PowerPC Transition

The 68060 was, in practical terms, the last word Motorola ever spoke in the 68k dialect. By the mid-1990s, the industry's center of gravity had shifted decisively toward reduced instruction set computing, and Motorola made the strategic decision to halt all development of the 680x0 architecture in 1994. The successor was PowerPC, a RISC-based design born from a collaborative effort among Motorola, IBM, and Apple Computer under the banner of the AIM alliance. This was not merely a product swap; it represented a philosophical break from the complex instruction set philosophy that had defined the 68k family for well over a decade. The 68060's superscalar pipeline, while technically impressive, could not match the cleaner execution models that RISC architectures offered at the time. Today, no mainstream computer ships with a 680x0-based processor, though derivative microcontrollers descended from the family continue to serve in embedded applications around the world.

A Vast Ecosystem, a Narrow Niche

The 68060 existed within a processor family whose reach was staggering. Across its lifetime, the 68k line powered Apple Macintosh computers, Commodore Amigas, Atari ST and Falcon machines, Sega Genesis and CD consoles, NeXT workstations, early Silicon Graphics IRIS systems, Sun Microsystems servers, AT&T UNIX PCs, Texas Instruments graphing calculators, Palm Pilot handhelds, and even radiation-hardened control systems aboard the Space Shuttle. Arcade boards from Sega, Capcom, and SNK also relied on 68k silicon. Yet the 68060 itself found a comparatively narrow deployment footprint. Notably, the Quantel Paintbox series of professional video-editing systems, which cycled through nearly every other 68k generation during its operational life beginning in 1981, never incorporated the 68060 into its hardware. The chip's late arrival and the industry's rapid pivot toward RISC architectures meant its superscalar innovations were deployed in far fewer systems than its predecessors had enjoyed.

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