Intel i960

Lore & Background

The i960 design was begun in response to the failure of Intel's iAPX 432 design of the early 1980s. In 1984, Intel and Siemens started a joint project, ultimately called BiiN, to create a high-end, fault-tolerant, object-oriented computer system programmed entirely in Ada. Intel's major contribution to the BiiN system was a new processor design, influenced by the protected-memory concepts from the i432. The first 960 processors entered the final stages of design in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986. The BiiN effort eventually failed, due to market forces, and the 960 was left without a use. Glenford Myers attempted to save the design by extracting several subsets of the full capability architecture, but was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor. The chip found a ready market in early high-performance 32-bit embedded systems. The lead architect of i960 was superscalarity specialist Fred Pollack, who was also the lead engineer of the Intel iAPX 432 and the lead architect of the i686 chip, the Pentium Pro.

Reader's Guide

The i960 family features four distinct architectures designed for upward binary compatibility: Core, Numerics, Protected, and Extended. To avoid the performance issues that plagued the i432, the central instruction-set architecture was a RISC design. In the Extended architecture, the memory subsystem was 33-bits wide to accommodate a 32-bit word and a tag bit for hardware memory protection. The i960 followed the original Berkeley RISC design in its use of register windows. The i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations. The i960CA, announced in July 1989, is widely considered to have been the first single-chip superscalar RISC implementation. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU. The processor continues to be used for a few military applications.

Born from Failure: The BiiN Project

The i960 owes its existence to a spectacular design misstep. Intel's iAPX 432, conceived in the early 1980s to give languages like Ada and Lisp hardware-level support for tagged, protected, garbage-collected memory, ended up painfully slow due to its instruction-set complexity and multi-chip implementation. In 1984, Intel joined forces with Siemens on the BiiN initiative, aiming to build a fault-tolerant, object-oriented computer system written entirely in Ada for high-reliability customers such as banks, industrial controllers, and nuclear power plants. Glenford Myers, recruited from IBM, took the architectural lead while many original i432 engineers rolled up their sleeves. Intel's key contribution was a new processor that kept the i432's protected-memory philosophy but stripped away the features that had crippled performance. The first 960 designs reached taping-out in October 1985, and working silicon appeared by early 1986. When BiiN collapsed under market pressure, the 960 was left stranded. Myers lobbied Intel to market it as a general-purpose or Unix chip, even approaching Steve Jobs about the NeXT platform, but management declined. The chip ultimately found its natural home in high-performance 32-bit embedded systems. Fred Pollack, a superscalarity specialist who had also led the i432 and later the Pentium Pro, served as lead architect.

A Tiered RISC Architecture

The i960 family was structured around four levels of upward binary compatibility. The Core tier provided a RISC-like instruction set; the Numerics tier layered on floating-point capability; the Protected tier added paged memory management, supervisor and user protection, string instructions, process scheduling, interprocess communication for operating systems, and symmetric multiprocessing; and the Extended tier brought object-level protection and application-level interprocess communication. The central design goal was to sidestep the instruction-set bloat that had doomed the i432, so the core ISA was deliberately RISC. In several respects the design tracked the original Berkeley RISC blueprint, most notably its use of register windows—implementation-specific caches holding per-subroutine registers that made subroutine calls and returns exceptionally fast. This stood in contrast to the Stanford MIPS approach, which delegated call-and-return optimization to the compiler. The Extended architecture widened the memory subsystem to 33 bits, carrying a 32-bit word plus a dedicated tag bit for hardware-enforced memory protection. Most variants shared a flat 32-bit address space with no segmentation, though the Extended tier could address up to 2 to the 26th power objects, each as large as 2 to the 32nd power bytes. The architecture also anticipated superscalar execution, allowing instructions to be dispatched simultaneously to multiple internal processing units.

Embedded Success and an Abrupt Corporate Sunset

During the early 1990s the i960 became one of the best-selling CPUs in the embedded microcontroller segment, trading blows with AMD's 29000 in a market hungry for capable 32-bit RISC cores. Its tiered feature set and RISC efficiency made it a natural fit for high-performance embedded applications, a niche the original BiiN ambitions had never reached. Yet the processor's commercial lifespan was severed in the late 1990s by a corporate decision rather than by technological obsolescence. As part of a settlement with Digital Equipment Corporation, Intel received the rights to manufacture the StrongARM CPU and consequently dropped the i960 from its marketing portfolio. The chip did not, however, disappear entirely. It continued to serve a small number of military applications, a domain where its compliance with MIL-STD-883C, its fault-tolerant design features, and its support for standards like the Joint Industrial Avionics Working Group 32-bit ISA kept it operationally relevant well beyond the point at which the commercial market had moved on. The i960's arc is thus one of genuine market triumph followed by an externally imposed, almost abrupt retirement.

Variants, the No-Connect Mystery, and Military Hardware

The i960 family shipped across several variants mapped to its architecture tiers, and some of them carry quirks that still puzzle engineers. The 80960KA (Core) and 80960KB (Numerics) were, despite their distinct marketing labels, internally identical silicon—only the designation on the package differed. Both contained more than 350,000 transistors, making them far larger and more costly to fabricate than their nominally supported feature sets actually required. The 80960MC (Protected) packed in an on-chip memory management unit, 32 general-purpose 32-bit registers, a 512-byte instruction cache, a stack frame cache, a high-speed 32-bit multiplexed burst bus, and an interrupt controller offering 256 vectors across 32 priority levels. It could be paired with Intel's M82965 Bus Extension Unit to build fault-tolerant systems, and both chips met the MIL-STD-883C military standard. A long-standing curiosity: 53 of the MC's 132 pins were marked no-connect, which led some to suspect hidden BiiN features. In reality the die simply lacked bond pads for those pins. The 80960XA (Extended) targeted military avionics, implementing object-oriented programming through a hardware tag bit and conforming to the JIAWG 32-bit ISA standard.

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