MIPS architecture processors

Lore & Background

The MIPS project began in 1981 at Stanford University under John L. Hennessy to investigate RISC technology. In 1984, Hennessy founded MIPS Computer Systems, and the first implementation, the R2000, was announced in 1985. The R2000 had thirty-one 32-bit general-purpose registers, no status register, and support for up to four co-processors, one of which handled exceptions, traps, and memory management. The R3000, released in 1988, added caches and multiprocessing support, becoming the first successful MIPS design. The R4000 series (1991) extended MIPS to 64-bit and moved the FPU onto the main die, achieving 100 MHz at introduction through deep pipelining. Quantum Effect Devices, founded by former MIPS employees, designed the R4600, R4700, R4650, and R5000, emphasizing large caches over raw clock speed. The R8000 (1994) was the first superscalar MIPS design, spread over six chips, and the R10000 (1995) introduced out-of-order execution on a single chip. Later cores based on the R10000 include the R12000, R14000, R16000, and R16000A. The R6000, an ECL implementation by Bipolar Integrated Technology, introduced the MIPS II architecture but did not deliver promised performance and quickly disappeared from the mainstream market.

Reader's Guide

The MIPS architecture's significance lies in its longevity and adaptability across markets. From its origins as a Stanford research project, it became the foundation for Silicon Graphics workstations and servers, Digital Equipment Corporation's DECstation line, and later for embedded systems, networking equipment, and game consoles such as the Sony PlayStation and Nintendo 64. The decision to license the architecture to third-party vendors in the early 1990s proved successful due to the core's simplicity, enabling companies like IDT, Toshiba, NEC, and Quantum Effect Devices to produce variants for specific applications. The architecture's lack of a status register, a design choice to avoid a potential bottleneck, was shared with the AMD 29000, DEC Alpha, and RISC-V. MIPS processors have been used in Cisco routers, WebTV set-top boxes, handheld PCs running Windows CE, and even outer-space missions via the radiation-hardened Mongoose-V. The architecture's evolution from 32-bit to 64-bit, from scalar to superscalar and out-of-order execution, and from multi-chip to single-chip designs demonstrates its ability to adapt to changing technological demands while maintaining backward compatibility.

Did You Know?

• The R2000 could be booted either big-endian or little-endian.
• The R3000A running at 40 MHz delivered 32 million instructions per second (MIPS), or VAX Unit of Performance (VUPs).
• The R8000 was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle.
• The R10000 introduced out-of-order execution and had larger 32 KB primary instruction and data caches.

Origins and the R4000 Era

The MIPS architecture first appeared in 1985 alongside the R2000 microprocessor, both created by MIPS Computer Systems. The name itself is a backronym standing for "Microprocessor without Interlocked Pipelined Stages," reflecting its RISC philosophy. When MIPS II arrived, the original was retroactively labeled MIPS I. The R6000, the first MIPS II chip in 1989, was built for servers but became a commercial disappointment. The real breakthrough came with the R4000 in 1991, the first MIPS III implementation, aimed at personal computers, workstations, and servers. MIPS Computer Systems pushed hard to make MIPS the dominant PC platform through the ACE consortium and the ARC standard, but that vision largely failed in the consumer space. The R4000 and its R4400 derivative found their true home in workstations and servers, with Silicon Graphics as the biggest customer. The R4300i, a derivative made by NEC, ended up inside the Nintendo 64, while the PlayStation also relied on MIPS processors, making gaming consoles among the highest-volume MIPS users of the mid-1990s.

Architectural Extensions and the MIPS32/64 Reorganization

One of MIPS's distinguishing traits was its family of optional extensions that let implementors tailor chips to specific workloads. MIPS-3D offered a compact set of floating-point SIMD instructions aimed squarely at 3D graphics. MDMX, sometimes called MaDMaX, provided a broader integer SIMD instruction set operating on 64-bit floating-point registers. MIPS16e compressed the instruction stream to shrink memory footprint, while MIPS MT introduced multithreading capability. The architecture also followed a strict superset rule: each new version contained everything from the previous one. That property, however, proved cumbersome. After MIPS Technologies separated from Silicon Graphics in 1998, the company restructured the architecture into two parallel tracks—MIPS32 and MIPS64—both introduced in 1999. MIPS32 drew from MIPS II with select features from later versions, while MIPS64 was grounded in MIPS V. The current iteration, MIPS32/64 Release 6 as of April 2017, adds a privileged kernel-mode System Control Coprocessor beyond the user-mode architecture. Notably, Release 4 was skipped entirely because the number four carries unlucky connotations in many Asian cultures.

The Unfulfilled MIPS V and the H1/H2 Cancellation

MIPS V was announced on October 21, 1996, at the Microprocessor Forum, alongside the MDMX extension. Its central goal was to accelerate 3D graphics transformations, a critical need given that Silicon Graphics' graphics workstations were a major non-embedded market for MIPS chips in the mid-1990s. The design paired the MIPS V instruction set with the integer-only MDMX extension to form a complete system for 3D graphics performance. Despite this ambition, no MIPS V implementation ever shipped. Silicon Graphics announced the H1 ("Beast") and H2 ("Capitan") microprocessors on May 12, 1997, with the H1 slated as the first MIPS V chip, expected in early 1999. The two projects were later merged and ultimately canceled in 1998. The MIPS V specification did not vanish entirely, though. MIPS64 Release 1, introduced in 1999, was based on MIPS V and preserved all of its features as an optional Coprocessor 1 (FPU) feature known as Paired-Single. This meant the architectural ideas lived on in the 64-bit line even though a dedicated MIPS V product never reached the market.

Legacy, Education, and the RISC-V Transition

MIPS left a deep imprint on both academia and the broader RISC landscape. Computer architecture courses at universities and technical schools around the world regularly use the MIPS instruction set as a teaching platform, and the architecture is widely credited with heavily influencing later RISC designs, most notably the Alpha processor. In the commercial world, MIPS processors powered a remarkable range of systems: from NEC and Pyramid Technology workstations to Tandem Computers servers, from supercomputers to the Emotion Engine inside Sony's PlayStation 2 (via the R5900, a Toshiba derivative of the R5000). After the 1998 spinout, MIPS Technologies pivoted toward the embedded market, licensing MIPS64 to companies including NEC, Toshiba, SiByte (later acquired by Broadcom), Philips, Cavium, Loongson Technology, and Ingenic Semiconductor. In December 2018, Wave Computing, then the new owner, announced the MIPS Open initiative to open-source the ISA. Yet in March 2021, MIPS made the definitive announcement that MIPS architecture development had ended, as the company shifted its focus to RISC-V, closing a chapter that had spanned more than three and a half decades.

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