NVAX
A CMOS VAX microprocessor used in late-model DEC systems.
The NVAX is a CMOS microprocessor from Digital Equipment Corporation (DEC) that runs the VAX instruction set. It powered late-model VAX systems introduced in 1991, such as the MicroVAX 3100, VAXstation 4000, VAX 4000, VAX 6000, VAX 7000/10000, and VAXft. A variant called the NVAX+ shares the same microarchitecture but uses a different bus interface and external cache; its bus matches the DECchip 21064, so it can be swapped out for an Alpha processor.
The NVAX die measures 16.2 by 14.6 mm (236.52 mm²) and contains 1.3 million transistors, built on DEC’s CMOS-4 process—a 0.75 μm process with three aluminum interconnect layers. It comes in a 339-pin pin grid array. Clock speeds for the NVAX are 83.3 MHz (12 ns), 71 MHz (14 ns), and 62.5 MHz (16 ns), delivering about 25 VAX Units of Performance (VUPs). The NVAX+ runs at 90.9 MHz (11 ns) and achieves roughly 35 VUPs, just shy of the VAX 9000 mainframe’s 40 VUPs, but in a desktop form factor. Its 431-pin array and cache system are identical to those on the Alpha, enabling a CPU-level upgrade.
The final model, the NVAX++ (also called NV5), appeared in 1994 in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operates at 133 MHz (7.5 ns) on DEC’s CMOS-5 process (0.50 μm) and reaches 50 VUPs. A 170.9 MHz NV5 followed in 1996, used in VAX 7000/10000 Model 8x0 systems. After the NV5, DEC moved entirely to the Alpha architecture.
The NVAX’s microarchitecture splits the processor into five semi-autonomous units: the I-box, E-box, F-box, M-box, and C-box. It is macropipelined, handling multiple VAX macroinstructions in parallel, each unit having its own micropipeline. The I-box fetches and decodes instructions, using a 2 KB direct-mapped virtual instruction cache (VIC) and a 512-entry by 4-bit branch history table, aiming to fetch eight bytes per cycle. The E-box executes most non-floating-point instructions, controlled by microcode from a 1,600-word control store with 20 patchable words. The F-box handles floating-point and 32-bit integer multiply instructions, featuring a four-stage pipeline for floating-point and integer multiply, plus a non-pipelined floating-point divider.
- Transistor count
- 1.3 million
- Die size
- 16.2 × 14.6 mm (236.52 mm²)
- Process
- CMOS-4, 0.75 μm, three layers of aluminium interconnect
- Package
- 339-pin pin grid array (NVAX); 431-pin array (NVAX+)
- Clock speeds
- 83.3 MHz (12 ns), 71 MHz (14 ns), 62.5 MHz (16 ns) for NVAX; 90.9 MHz (11 ns) for NVAX+
- Performance
- 25 VUPs (NVAX); 35 VUPs (NVAX+)
Lore & Background
The NVAX and NVAX+ were introduced in 1991 and used in a range of VAX systems from the MicroVAX 3100 to the VAXft. The NVAX+ was designed with a bus and cache system identical to those on the DECchip 21064 Alpha processor, enabling a system to be upgraded from NVAX+ to Alpha by changing only the CPU. The NVAX offered about 25 VUPs, while the NVAX+ ran at roughly 35 VUPs, only slightly less than the VAX 9000 mainframe's roughly 40 VUPs, but in a desktop form factor.
The final model in the series was the NVAX++ (also known as NV5), introduced in 1994 in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in Digital's CMOS-5 process (0.50 μm), achieving 50 VUPs. In 1996, a 170.9 MHz NV5 was used in the VAX 7000/10000 Model 8x0. The NVAX++ was the last VAX processor; DEC had moved entirely to the DEC Alpha after that point.
Reader's Guide
The NVAX and its variants represent the final generation of DEC's VAX microprocessor line, bridging the transition from the VAX architecture to the Alpha architecture. The NVAX+ was notable for its bus compatibility with the DECchip 21064, allowing a straightforward CPU-level upgrade path from VAX to Alpha systems. The NVAX++ (NV5) achieved 50 VUPs, surpassing the performance of the VAX 9000 mainframe in a microprocessor form factor. Although Digital updated the design throughout the early 1990s, the processors and the VAX platform itself were ultimately superseded by the introduction of the DECchip 21064, an implementation of the Alpha architecture, and the resulting systems in November 1992. The NVAX series thus served as both the peak of VAX microprocessor performance and the last of its kind before DEC's complete shift to Alpha.
Did You Know?
- The NVAX+ used a bus and cache system identical to those on the DECchip 21064 Alpha, allowing a system to be upgraded by changing only the CPU.
- The NVAX++ (NV5) was the last VAX processor, operating at 133 MHz and later 170.9 MHz.
- The NVAX die measured 16.2 by 14.6 mm and contained 1.3 million transistors.
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