NCR/32
Externally microprogrammable 32-bit chipset from NCR.
The NCR/32 VLSI Processor family, a 32-bit architecture and chipset from NCR Corporation, debuted in the early 1980s and was primarily used in minicomputers. Its standout feature was external microprogrammability, which let designers craft custom instructions for specific tasks. NCR announced the initial four-chip set in the third quarter of 1982. The central processor chip had an external microcode bus, enabling custom microcode that could emulate NCR’s earlier mainframes or an IBM System/370. This design also allowed high-level languages like Prolog and polyFORTH to execute directly from custom instructions in an external microcontrol store. Although some have called the NCR/32 a reduced instruction set computer (RISC) system, that label is debated: the original Berkeley RISC and Stanford MIPS research projects didn’t finish until 1984, and avoiding microcode was a key RISC principle.
NCR used the architecture in its own computer models, communications peripherals, and at least one board-level product. Some designers later left NCR to found Celerity Computing, which used the NCR/32 in its minicomputers running a version of Berkeley’s Unix Release 4.2.
The chipset included the NCR/32-000 Central Processor Chip (CPC), the NCR/32-010 Address Translation Chip (ATC), the NCR/32-020 Extended Arithmetic Chip (EAC), the NCR/32-500 System Interface Controller (SIC), the NCR/32-580 System Interface Transmitter (SIT), and the NCR/32-590 System Interface Receiver (SIR). The CPC was the core; all other devices were optional. It contained 40,000 transistors, originally built on a 3-micron NMOS process. It supported two microcode levels: vertical microcode stored in an external 128K-byte Instruction Storage Unit (ISU), and horizontal microcode in an internal ROM encoding 179 operations in 95-bit-wide words. The CPC accessed the ISU over a 16-bit Instruction Storage Unit Bus (ISUBUS), feeding a three-stage microinstruction pipeline. Internally, it had a 32-bit ALU and sixteen 32-bit general-purpose registers. It could address up to 4 GB of direct virtual memory and 16 MB of direct real memory over a 32-bit Processor Memory Bus (PMBUS). Its base clock was 13.3 MHz, with a two-phase, non-overlapping clock giving a 150-nanosecond cycle time; 90% of microinstructions completed in one cycle.
Quick Facts
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Lore & Background
NCR announced the release of its NCR/32 architecture in the third quarter of 1982. The Central Processor Chip (CPC) included an external microcode bus that let a designer create custom instructions. This feature was used to develop microcode that allowed the NCR/32 to emulate NCR's earlier mainframe computers or an IBM System/370. The design also enabled high-level languages such as Prolog and polyFORTH to be executed directly from custom instructions in the external microcontrol store.
Both the NCR/32 processor and some products that used it have been called reduced instruction set computer (RISC) systems, although the description has been debated; the original Berkeley RISC and Stanford MIPS research programs did not complete until 1984, and avoiding the use of microcode was one of the key RISC design principles. Some of the designers of the NCR/32 left NCR for a new company, Celerity Computing, which used the NCR/32 in its own minicomputer designs, running a version of the University of California at Berkeley's Unix Release 4.2.
The chipset includes the NCR/32-000 CPC, NCR/32-010 Address Translation Chip, NCR/32-020 Extended Arithmetic Chip, NCR/32-500 System Interface Controller, NCR/32-580 System Interface Transmitter, and NCR/32-590 System Interface Receiver. The CPC consists of 40,000 transistors and supports two levels of microcode: vertical microcode stored in an external 128K-byte Instruction Storage Unit, and horizontal microcode stored in internal ROM encoding 179 operations in 95-bit wide words.
Reader's Guide
The NCR/32's significance lies in its external microprogrammability, a feature that allowed it to emulate earlier mainframe architectures and directly execute high-level languages. This made it a flexible platform for minicomputer systems, used in NCR's own 9300, 9400, 9800, and System 10000 models, as well as in communications peripherals like the Comten 5620 and board-level products such as the NCR/32-796A Multibus single-board computer. Celerity Computing adopted the chipset for its ACCEL architecture, including the C1200 minicomputer. The architecture's classification as RISC remains debated, as its use of microcode contradicted a key RISC principle, and the RISC research programs were still ongoing at the time of its release. Honeywell also signed an agreement to use the NCR/32 in its next-generation minicomputer. The chipset's memory management, arithmetic acceleration, and system interface chips provided a complete system solution, with the CPC able to address up to 4 GB of virtual memory and 16 MB of real memory.
Did You Know?
- The NCR/32 CPC could emulate an IBM System/370 via custom microcode.
- The chipset was originally fabricated in a 3 micron NMOS process, later reduced to 2 microns.
- 90% of the CPC's microinstructions completed in a single 150-nanosecond cycle.
- Some designers of the NCR/32 later founded Celerity Computing, which used the chip in its minicomputers.
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