ARM C-series

Lore & Background

The C-series family currently includes four performance tiers: Nano, Pro, Premium, and Ultra. Nano cores are in-order designs, while the other three tiers provide out-of-order execution. Each tier targets different performance, energy, and area efficiency requirements. The C1-series, introduced in September 2025, is the first CPU family built on the Armv9.3 architecture, which includes native support for SME2 for hardware acceleration of matrix operations used in AI and machine learning workloads.

The C1-Ultra is the flagship high-performance core, designed for demanding AI tasks and peak single-threaded performance. It features the widest micro-architecture in the industry and achieves significant performance improvements through double-digit instructions per cycle (IPC) gains, succeeding the Cortex-X925. The C1-Premium is described as ARM's first sub-flagship CPU, offering comparable performance to C1-Ultra in a significantly smaller area footprint, introducing a new tier. The C1-Pro is optimized for sustained performance across extended workloads such as gaming, video processing, and multitasking, emphasizing performance per watt and including enhanced branch prediction and memory system updates; it succeeds the Cortex-A725. The C1-Nano is the smallest and most power-efficient core, designed for always-on AI tasks, background processing, and low-power scenarios, particularly suited for wearables and compact consumer devices; it succeeds the Cortex-A520.

The C1-DSU serves as the interconnect and shared cache infrastructure for C-series CPU clusters, supporting the latest architectural features and including low-power optimizations for improved bandwidth scaling and power efficiency. The C-series CPUs are designed as part of the ARM Lumex compute subsystem (CSS) platform, which provides a complete reference design for mobile and consumer devices, allowing chip manufacturers to integrate cores with other ARM intellectual property and customize configurations.

Reader's Guide

The ARM C-series represents a significant branding shift for ARM's application processor lineage, replacing the long-standing Cortex-A and Cortex-X naming scheme with a tiered system (Nano, Pro, Premium, Ultra) that clearly delineates performance and efficiency targets. Its introduction in 2025 under the Armv9.3 architecture marks the first native integration of Scalable Matrix Extension 2 (SME2) across all cores, directly addressing the growing demand for on-device artificial intelligence capabilities in consumer and mobile devices. The C1-series, as the first family, establishes a new sub-flagship tier with the C1-Premium, offering a balance of high performance and area efficiency that did not exist in previous ARM generations. The C1-Ultra's claim of the widest micro-architecture in the industry and double-digit IPC gains over prior cores positions it as a direct successor to the Cortex-X925 for peak performance. The C1-Pro and C1-Nano continue the roles of their predecessors (Cortex-A725 and Cortex-A520) with updates to branch prediction, memory systems, and power efficiency. The C1-DSU interconnect and the Lumex CSS platform provide a complete reference design, enabling semiconductor companies to license synthesizable hardware descriptions and integrate C-series cores into custom system-on-chip designs optimized for specific process nodes and power targets. This family's legacy lies in its unified SME2 support across all tiers, making AI acceleration a standard feature rather than an optional add-on, and in its refined tier structure that offers more granular choices for device manufacturers.

Did You Know?

• All C-series cores implement the ARMv9.3-A architecture with integrated SME2.
• The C1-Ultra succeeds the Cortex-X925 and features the widest micro-architecture in the industry.
• The C1-Nano is designed for always-on AI tasks and low-power scenarios such as wearables.