Alpha 21364

Lore & Background

The Alpha 21364 was revealed in October 1998 by Compaq at the 11th Annual Microprocessor Forum, described as an Alpha 21264 with a 1.5 MB 6-way set-associative on-die secondary cache, an integrated Direct Rambus DRAM memory controller, and an integrated network controller for connecting to other microprocessors. The core was based on the EV68CB derivative of the Alpha 21264, with the only modification being a larger victim buffer quadrupled to 32 entries (16 for Dcache and 16 for Scache). The original schedule anticipated tape-out in late 1999, samples in early 2000, and volume shipments in late 2000, but delays pushed tape-out to April 2001. The microprocessor was introduced on 20 January 2002 when systems using it debuted. Unlike previous Alpha microprocessors, it was not sold on the open market.

The development focused on features improving memory performance and multiprocessor scalability, influenced by a forward-looking article titled "It's the Memory, Stupid!" by Richard L. Sites. The secondary cache (Scache) had a capacity of 1.75 MB, was 7-way set associative, and used a 64-byte line size with write-back policy and SECDED ECC. Access latency was 12 cycles, which observers considered significant; the latency was not reduced further as it would not have improved performance given the Alpha 21264 core's design for external SRAM. The two integrated memory controllers supported Rambus DRAM operating at two-thirds of the microprocessor's clock frequency, providing five RDRAM channels each (four for memory, one for RAID-like redundancy), yielding total memory bandwidth of 12.8 GB/s. The network router (R-box) connected to other microprocessors via four ports (North, South, East, West) and a fifth port for I/O, supporting up to 127 other microprocessors in shuffle or 2D torus topologies, implementing NUMA multiprocessing.

Reader's Guide

The Alpha 21364 represented a significant shift in microprocessor design by integrating memory controllers and a network router on-die, directly addressing the growing importance of memory subsystem performance as highlighted by Richard L. Sites. Its focus on multiprocessor scalability allowed systems to connect up to 128 microprocessors in a 2D torus topology, with each node having its own memory and I/O, enabling non-uniform memory access (NUMA) configurations. The integrated memory controllers included proprietary features such as keeping all 128 pages open to reduce latency and fault-tolerant capabilities. The microprocessor also supported lock-step operation for fault-tolerant computers, a feature resulting from Compaq's decision to migrate Tandem's Himalaya servers from MIPS to Alpha, though those machines never used it due to the later phase-out of Alpha in favor of Itanium. The Alpha 21364 was originally intended to be succeeded by the Alpha 21464 (EV8) with four-way simultaneous multithreading, but that project was cancelled on 25 June 2001. A further development, the Alpha 21364A (EV79), was cancelled on 23 October 2003, with HP citing performance and schedule issues, and was replaced by the EV7z.

Did You Know?

• The Alpha 21364 was not sold on the open market, unlike previous Alpha microprocessors.
• Its secondary cache had a 12-cycle latency, which observers considered significant but was not reduced further as it would not have improved performance.
• The microprocessor could connect to as many as 127 other Alpha 21364 processors using shuffle or 2D torus network topologies.
• The Alpha 21364 contained 152 million transistors and was fabricated by IBM in a 0.18 μm process.