Alpha 21264
A four-issue superscalar RISC microprocessor with out-of-order execution.
The Alpha 21264, codenamed EV6, is a RISC microprocessor from Digital Equipment Corporation that debuted on 19 October 1998 and implements the Alpha instruction set architecture. It is a four-issue superscalar design capable of out-of-order and speculative execution, with a peak throughput of six instructions per cycle and a sustained rate of four instructions per cycle. The processor uses a seven-stage pipeline.
At any moment, the chip can manage up to 80 instructions across various pipeline stages, more than any other microprocessor of its time. Decoded instructions wait in queues—20 entries for integers and 15 for floating-point—and are issued once their operands are ready. Each queue can issue as many instructions as there are pipelines available.
The integer execution unit, or Ebox, handles integer, load, and store operations. It contains two integer units, two load/store units, and two integer register files. Each register file holds 80 entries: 32 architectural registers, 40 rename registers, and 8 PAL shadow registers. Register R31 is absent because it is hardwired to zero and read-only in the Alpha architecture. Each register file is paired with one integer unit and one load/store unit, forming a cluster (U0 and U1). This clustering reduces the number of read and write ports, shrinking the register file’s physical size and enabling higher clock speeds. However, writes between clusters must be synchronized, costing one clock cycle and reducing performance by about one percent. This loss is offset by the higher clock frequency and by instruction issue logic that avoids synchronization by preferring instructions that do not depend on data from the other cluster.
The two clusters are nearly identical, but U1 includes a seven-cycle pipelined multiplier, while U0 has a three-cycle pipeline for Motion Video Instructions (MVI), a SIMD multimedia extension. The load/store units are simple arithmetic logic units that calculate virtual addresses for memory access and can also execute basic arithmetic and logic instructions when idle. The Ebox thus provides four 64-bit adders, four logic units, two barrel shifters, byte-manipulation logic, and two sets of conditional branch logic split between U0 and U1.
The floating-point unit, or Fbox, has two pipelines and a register file with 72 entries (32 architectural, 40 rename).
- Launch date
- 19 October 1998
- Transistor count
- 15.2 million
- Die size
- 313.96 mm²
- Fabrication process
- 0.35 μm CMOS with six levels of interconnect
- Package
- 587-pin ceramic interstitial pin grid array (IPGA)
- Peak execution rate
- 6 instructions per cycle
- Sustained execution rate
- 4 instructions per cycle
Lore & Background
The Alpha 21264 could have up to 80 instructions in various stages of execution at any given time, surpassing any other contemporary microprocessor. Decoded instructions are held in instruction queues and are issued when their operands are available; the integer queue contained 20 entries and the floating-point queue 15. The Ebox executes integer, load and store instructions and has two integer units, two load store units and two integer register files, each containing 80 entries (32 architectural, 40 rename, 8 PAL shadow registers). The register files are organized into two clusters designated U0 and U1, a scheme that reduced the number of write and read ports and enabled higher clock frequencies, though writes to register files required synchronization costing one percent performance. The Fbox executes floating-point instructions with two pipelines and a 72-entry register file (32 architectural, 40 rename). The primary cache is split into 64 KB instruction and data caches, with the D-cache dual-ported by transferring data on both clock edges. The secondary B-cache is external, ranging from 1 to 16 MB, controlled by the microprocessor and implemented with SSRAM. Branch prediction uses a tournament algorithm with local, global, and choice predictors. The external interface includes a bidirectional 64-bit DDR data bus and two 15-bit unidirectional address/control buses; Digital licensed this bus to AMD, where it became known as the EV6 bus and later evolved to HyperTransport.
Reader's Guide
The Alpha 21264's significance lies in its advanced out-of-order execution capability, allowing up to 80 instructions in flight, which was unmatched among contemporary microprocessors. Its clustered integer register file design reduced physical size and enabled higher clock frequencies, though it introduced a synchronization penalty that was offset by the clock speed gain and intelligent instruction issue logic. The tournament branch predictor, developed at Digital's Western Research Laboratory, addressed the microprocessor's minimum seven-cycle branch misprediction penalty. The external EV6 bus was licensed to Advanced Micro Devices and used in their Athlon microprocessors, later evolving into HyperTransport, demonstrating the design's influence beyond Digital's own products. The Alpha 21264 supported 48-bit or 43-bit virtual addresses and a 44-bit physical address, allowing up to 16 TiB of physical memory, a significant increase over previous Alpha CPUs. A derivative, the Alpha 21264A (EV67), was introduced in late 1999 as a shrink of the original design, with versions ranging from 600 to 833 MHz.
Did You Know?
- The integer register file contained 80 entries, with no entry for register R31 because it is hardwired to zero.
- The D-cache is dual-ported by transferring data on both the rising and falling edges of the clock signal.
- Digital Equipment Corporation licensed the external bus to AMD, where it was known as the EV6 bus.
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