Xeon Phi

Lore & Background

The Xeon Phi product line originated from Intel's Larrabee microarchitecture, in development since 2006, which introduced very wide 512-bit SIMD units to an x86-based processor design. The Larrabee project to produce a retail GPU product was terminated in May 2010. Intel's Many Integrated Core (MIC) prototype board, named Knights Ferry, was announced on 31 May 2010, incorporating a processor codenamed Aubrey Isle with 32 in-order cores at up to 1.2 GHz, four threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache, built at a 45 nm process. The prototype boards only supported single-precision floating-point instructions.

The first commercial product, Knights Corner, was made at a 22 nm process using Intel's Tri-gate technology with more than 50 cores per chip. On 18 June 2012, Intel announced that Xeon Phi would be the brand name for all products based on their Many Integrated Core architecture. The Xeon Phi coprocessor's core featured a vector processing unit (VPU) with a novel 512-bit SIMD instruction set known as Intel Initial Many Core Instructions (IMCI), capable of executing 16 single-precision or 8 double-precision operations per cycle, and supporting Fused Multiply-Add (FMA) instructions. The VPU also included an Extended Math Unit (EMU) for operations such as reciprocal, square root, and logarithm.

A second-generation product, codenamed Knights Landing, was announced in June 2013. These chips could be used as a standalone CPU rather than just as an add-in card, and were manufactured using Intel's 14 nm process technology. Knights Landing contained up to 72 Airmont (Atom) cores with four threads per core, using the LGA 3647 socket and supporting up to 384 GB of memory. The Xeon Phi product line aimed to compete with Nvidia's Tesla and AMD Radeon Instinct lines, targeting machine learning and GPGPU use cases. It was discontinued due to a lack of demand and Intel's problems with its 10 nm node.

Reader's Guide

The Xeon Phi line represented Intel's attempt to bridge the gap between traditional x86 CPUs and GPUs for high-performance computing. Its key significance lay in its x86 compatibility, which allowed software originally written for standard x86 CPUs to run with less modification compared to GPGPUs like Nvidia Tesla. This made it attractive for supercomputing centers that wanted to leverage existing codebases and parallelization tools such as OpenMP, OpenCL, and Cilk Plus. The Tianhe-2 supercomputer, which used Xeon Phi coprocessors alongside Ivy Bridge-EP Xeon processors, was the world's fastest from 2013 until November 2015, achieving 33.86 petaFLOPS. However, the Xeon Phi coprocessors were eventually phased out by the end of 2017 and replaced by custom-built Matrix-2000 coprocessors in Tianhe-2. The product line's legacy includes its pioneering use of 512-bit SIMD instructions, which influenced later AVX-512 extensions, and its demonstration of manycore x86 architectures for supercomputing. Its discontinuation reflected both market dynamics and Intel's manufacturing challenges with its 10 nm node.

Did You Know?

• The Xeon Phi architecture was originally based on Intel's cancelled Larrabee GPU design.
• The Tianhe-2 supercomputer used Xeon Phi coprocessors and was the world's fastest from 2013 until November 2015.
• The Xeon Phi's vector processing unit featured a 512-bit SIMD instruction set called Intel Initial Many Core Instructions (IMCI).