Single-chip Cloud Computer

Lore & Background

The SCC was developed as part of an Intel research project into multi-core processors and parallel processing. Its name reflects the concept of integrating cloud-computing data center architecture into a single chip. The chip comprises 48 P54C Pentium cores connected by a 4×6 2D-mesh of 24 tiles arranged in four rows and six columns. Each tile contains two cores and a 16 KB message passing buffer (MPB) shared by the two cores, which functions as a router enabling direct core-to-core communication without routing through main memory.

The SCC contains 1.3 billion 45 nm transistors and uses 25 to 125 watts of power depending on processing demand. It includes four DDR3 memory controllers connected to the 2D mesh, capable of addressing 64 GB of random-access memory. The chip operates in two modes: processor mode, where cores are active executing code from system memory; and mesh mode, where cores are turned off and only routers, transistors, and RAM controllers remain active to send and receive large data packets without a memory map.

Intel intended to share this technology with other companies, including HP, Yahoo, and Microsoft, to foster collaborative research. The goal was to make the SCC scalable to 100+ cores, potentially by enabling communication between individual chips. Intel aimed to enhance parallel programming productivity and power management, leveraging the chip's architecture and numerous cores.

Reader's Guide

The SCC was utilized for research purposes as of 2010, running the Linux operating system on the chip but not Windows. Its applications included web servers, data informatics, bioinformatics, and financial analytics. The chip's architecture, with cores spread across the chip but capable of direct communication, allowed it to resemble a network of cloud computers. Proper coding integration resulted in a functional processor with high speed, power, and energy efficiency.

Intel intended to share the technology with HP, Yahoo, and Microsoft to advance collaborative research, with the goal of scaling the SCC to 100+ cores. Further experimentation was planned on this architecture and similar chip architectures to develop many-core scalable processors that maximize processing power while maintaining energy efficiency. As of September 2025, a software package named sccKit, which was publicly available about ten years earlier with programs to communicate directly to the SCC, was available at the Internet Archive after its original website became defunct.

Did You Know?

• The SCC contains 48 P54C Pentium cores arranged in a 4×6 2D-mesh of 24 tiles.
• Each tile has two cores and a 16 KB message passing buffer shared by the cores, functioning as a router.
• The chip can run Linux but cannot run Windows.
• As of September 2025, the sccKit software package was available at the Internet Archive.