Intel 8087
First floating-point coprocessor for the Intel 8086 line.
The Intel 8087, launched in 1980, was the first math coprocessor designed for the 8086 family of CPUs. Its job was to accelerate floating-point math like addition, subtraction, multiplication, division, and square roots, as well as transcendental functions such as exponentials, logarithms, and trigonometry. Depending on the software, speed gains ranged from roughly 20% to over 500%. The chip managed about 50,000 FLOPS while consuming around 2.4 watts.
The 8087 pushed the limits of chip fabrication at the time. Even basic operations like addition and subtraction could take over 100 machine cycles, and some instructions needed more than 1,000 cycles. It lacked a hardware multiplier, relying instead on the CORDIC algorithm for calculations. Sales got a big lift when the 1981 IBM PC motherboard included a dedicated socket for it. Development of the 8087 helped shape the IEEE 754-1985 standard for floating-point arithmetic. Available speed grades were 4.77 (5), 8, and 10 MHz. Later x87 coprocessors appeared for the 80186, 80286, 80386, 80386SX, and 80486SX processors. Starting with the 80486DX, Intel integrated floating-point units directly into the CPU. The 486SX had a disabled or missing FPU but could use a separate 80487, which was essentially a 486DX with an extra pin to disable the main processor.
Intel had previously made the 8231 arithmetic processing unit and the 8232 floating-point processor for 8080-like systems, using an 8-bit data bus and interfacing via programmed I/O or DMA. The 8087 was first envisioned by Bill Pohlman, the engineering manager behind the 8086, who ensured the 8086 design could support a future math chip. In 1977, Pohlman got approval to design the 8087. Bruce Ravenel served as architect, and John Palmer was hired as co-architect and mathematician. They created a revolutionary design featuring 64 bits of mantissa and 16 bits of exponent for the longest real-number format, a stack-based CPU with eight 80-bit stack registers, and a rich instruction set. This solved long-standing issues in numerical computing: rounding errors were eliminated for 64-bit operands, and numerical mode conversions were handled for all 64-bit numbers. Palmer credited William Kahan’s writings on floating-point as a major influence.
The 8087’s aggressive design initially met resistance in Santa Clara.
Quick Facts
- Slowest
- 4
- Slow-Unit
- MHz
- Fastest
- 10
- Transistors
- 65000
- Soldby
- Intel, IBM
- Designfirm
- Intel
- Arch
- x87 (coprocessor extension of x86-16)
- Predecessor
- 8231/8232
- Successor
- 80287
Facts from the source article.
Lore & Background
The 8087 was initially conceived by Bill Pohlman, the engineering manager at Intel who oversaw the development of the 8086 chip. In 1977, Pohlman got the go-ahead to design the math chip. Bruce Ravenel was assigned as architect, and John Palmer was hired as co-architect and mathematician. They devised a design with 64 bits of mantissa and 16 bits of exponent for the longest-format real number, a stack architecture CPU, and eight 80-bit stack registers. The design solved rounding-error problems for 64-bit operands and numerical mode conversions for all 64-bit numbers. Palmer credited William Kahan's writings on floating point as a significant influence. The design initially met a cool reception in Santa Clara due to its aggressive nature, but was eventually assigned to Intel Israel, with Rafi Nave leading implementation. Palmer, Ravenel, and Nave were awarded patents for the design; Robert Koehler and John Bayliss also received a patent for the technique where instructions with a particular bit pattern were offloaded to the coprocessor. The 8087 had 65,000 transistors and was manufactured as a 4.5 μm (later shrunk to 3 μm) depletion-load HMOS circuit. To reduce silicon size, microcode was implemented in multilevel ROM storing 2 bits per location using one of four possible currents. The device introduced about 60 new instructions, most assembly mnemonics beginning with F (e.g., FADD, FMUL, FCOM). Binary encodings for all 8087 instructions begin with the bit pattern 11011 (decimal 27, the ASCII character ESC). The 8087 was expensive and difficult to manufacture, with low yields, and ran hot, requiring a ceramic package for thermal dissipation.
Reader's Guide
The 8087's development led to the IEEE 754-1985 standard for floating-point arithmetic. Sales received a significant boost when a coprocessor socket was included on the 1981 IBM PC motherboard. The 8087 worked in tandem with the 8086 or 8088, executing instructions in parallel: while the main CPU handled integer operations, the 8087 performed floating-point calculations. The main CPU executed the ESC instruction, and the 8087 observed the bus, decoding the instruction stream in sync. For memory operands, the 8087 could use DMA to take control of the bus for additional data transfers. The WAIT instruction of the main CPU was provided to ensure the 8087 had completed its previous instruction before receiving a new one. The 8087 maintained its own prefetch queue, synchronized with the CPU via queue-status signals. Later x87 coprocessors were produced for the 80186, 80286, 80386, 80386SX, and 80486SX processors. Starting with the 80486DX, Intel x86 processors featured integrated floating-point units; the 80486SX had a disabled or absent FPU but allowed a separate 80487, which was essentially a 486DX with an extra pin to disable the existing CPU.
Did You Know?
- The 8087 could perform about 50,000 FLOPS using around 2.4 watts.
- The chip lacked a hardware multiplier and implemented calculations using the CORDIC algorithm.
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