Intel 80387SX

Lore & Background

The 80387SX was introduced in 1987 as the coprocessor for the Intel 80386SX microprocessor. It was designed only to work with the 386SX, rather than the standard 386DX, because the original 80387 could not communicate with the altered 16-bit data bus of the 386SX, which was modified from the original 386DX's 32-bit data bus. The 387SX uses a 68-pin PLCC socket, like some variants of the 80286 and the less common 80186 CPU, and was made in speeds ranging from 16 MHz to 33 MHz, matching the clock speed range of Intel-manufactured 386SX CPUs. Some chips like the IIT 3C87SX could reach up to 40 MHz, matching the clock speeds of the fastest 386SX CPUs.

With the 386SX/387SX combination, it provides three to five times the floating-point performance compared to the 80286/80287 combination. Intel released a low-power version of the 387SX coprocessor. A boxed version of the 387SX was available for US$506. In 1991, the 25-MHz Intel387 SX coprocessor had a manufacturer's suggested retail price of US$189. In 1993, the 33-MHz Intel387 SX coprocessor had a manufacturer's suggested retail price of US$109.

Reader's Guide

The Intel 80387SX holds significance as the dedicated floating-point coprocessor for the Intel 80386SX, enabling hardware-based floating-point arithmetic for systems built around that CPU. Its introduction in 1987 addressed the compatibility issue between the original 80387 and the 386SX's narrower 16-bit data bus, ensuring that users of the 386SX could still benefit from hardware floating-point acceleration. The 387SX's performance, offering three to five times the floating-point performance of the 80286/80287 combination, made it a notable upgrade for computational tasks. The availability of a low-power version and pricing that decreased over time—from a boxed version at US$506 to a 33-MHz model at US$109 in 1993—reflected its role in the evolving PC market. Third-party chips like the IIT 3C87SX extended its speed range to 40 MHz, matching the fastest 386SX CPUs. Its legacy lies in enabling floating-point operations for a key transitional processor line, bridging the gap between earlier 16-bit systems and the later dominance of integrated FPUs.