HyperTransport

Lore & Background

HyperTransport was introduced on April 2, 2001, and is managed by the HyperTransport Consortium. It operates as a double data rate (DDR) connection, sending data on both rising and falling clock edges, with autonegotiated frequency and bit width ranging from 2 to 32 bits per link. Each HyperTransport bus consists of two unidirectional links. Version 3.1 supports a maximum clock of 3.2 GHz, yielding 6400 MT/s and up to 25.6 GB/s per direction with full 32-bit links. Links of different widths can be mixed in a single system, and link splitting allows a 16-bit link to be divided into two 8-bit links. Electrically, HyperTransport uses low-voltage differential signaling (LVDS) at 1.2 V; version 2.0 added post-cursor transmitter deemphasis, and version 3.0 added scrambling, receiver phase alignment, and optional transmitter precursor deemphasis.

HyperTransport is packet-based, with each packet composed of 32-bit words. The first word contains a command field; many packets include a 40-bit address, with an additional 32-bit control packet for 64-bit addressing. Data payloads are padded to multiples of 32 bits. The technology supports posted and non-posted writes, reads, system management messaging, interrupts, probes, I/O transactions, and the PCI consumer/producer ordering model. It also facilitates power management in compliance with the Advanced Configuration and Power Interface specification, and version 3.0 added capabilities for a centralized power management controller.

Reader's Guide

HyperTransport's primary significance lies in replacing the Intel-defined front-side bus with an open, scalable interconnect. Unlike Intel's proprietary front-side bus, which requires different interfaces for each processor type and RAM speed, HyperTransport is an open specification published by a multi-company consortium. A single HyperTransport adapter chip works with a wide spectrum of HyperTransport-enabled microprocessors. AMD used HyperTransport to replace the front-side bus in its Opteron, Athlon 64, Athlon II, Sempron 64, Turion 64, Phenom, Phenom II, and FX families, and also replaced the back-side bus in its dual-core and later families. For multiprocessor systems, AMD employed HyperTransport with a proprietary cache coherency extension as part of its Direct Connect Architecture in Opteron and Athlon 64 FX processors; the Infinity Fabric used with EPYC server CPUs is a superset of HyperTransport. The technology also found use as a router or switch bus, as a co-processor interconnect (with FPGAs from Altera and Xilinx directly supporting the interface), and through the HTX and HTX3 add-on card connectors, which allow slot-based peripherals direct CPU access. The current specification HTX 3.1 remained competitive for 2014 high-speed DDR4 RAM and slower flash RAM, offering a wider range of RAM speeds on a common CPU bus than any Intel front-side bus.

Did You Know?

• HyperTransport was originally called Lightning Data Transport.
• It is a double data rate connection, sending data on both rising and falling clock edges.
• HyperTransport supports autonegotiated bit widths from 2 to 32 bits per link.
• The HyperTransport Consortium is the governing body for the technology.