Xeon D

Lore & Background

The Xeon D was designed to offer better performance per watt compared to the Xeon E3 and better absolute performance compared to the Atom processors, while operating at lower power and higher densities than Xeon E5 processors. Particularly, the Xeon D was designed to compete with emerging ARM microarchitecture–based server solutions, by offering superior single core performance. The first generation used the Broadwell microarchitecture, with all models designed for the SoC Server market segment and the FCBGA1667 interface, equipped with dual-channel DDR4 up to 128GB with ECC support.

The Skylake-based Xeon D-2100 products were released in February 2018, bringing an increased maximum number of cores, the Skylake microarchitecture, AVX-512 acceleration, and cryptographic acceleration. The second generation also offered increased clock speeds, resulting in greater performance, though the maximum thermal design power also increased. However, the level of AVX-512 support is unclear by product, with higher end products having greater performance than the listed specifications. Intel announced a second generation of Xeon D products to succeed the Broadwell (D-1500) series, codenamed Hewitt Lake, in February 2019.

Intel announced the next generation of Xeon D, codenamed Ice Lake-D, in April 2021. Intel officially launched the Xeon D D-2700 series and D-1700 series CPUs at MWC 2022. The Xeon D D-2800 series and D-1800 series were announced on December 14, 2023. Early 2025, the Xeon 6 SoC line was announced as the 'next gen' for at least a part of the Xeon D lineup.

Reader's Guide

The Xeon D line occupies a distinct niche in Intel's server processor lineup, bridging the gap between low-power Atom processors and higher-power Xeon E5 processors. Its design goals emphasized better performance per watt than the Xeon E3 and better absolute performance than Atom, while operating at lower power and higher densities than Xeon E5. This positioning was specifically intended to compete with emerging ARM-based server solutions by offering superior single-core performance. The integration of network interface controllers, a PCIe root complex, and USB and SATA controllers directly on the SoC made it particularly suitable for microserver and edge applications where space and power are constrained. Over its generations, the Xeon D evolved from Broadwell through Skylake, Hewitt Lake, and Ice Lake-D, each adding improvements in core counts, clock speeds, and features such as AVX-512 and cryptographic acceleration. The announcement of the Xeon 6 SoC line in early 2025 as the 'next gen' for at least part of the Xeon D lineup indicates that the platform continues to be developed, maintaining its relevance in the microserver and edge computing markets.

Did You Know?

• The Xeon D was announced in 2014 and first released in 2015.
• The Skylake-based Xeon D-2100 series was released in February 2018.

System-on-Chip Thinking for the Edge

Xeon D was conceived as a fundamentally different kind of server processor. Rather than following the traditional path of pairing a CPU with a separate platform controller hub and discrete I/O components, Intel baked network interface controllers and other I/O blocks directly into the silicon. This system-on-chip approach meant that a Xeon D board could operate without the separate southbridge chip that conventional server designs required. The target was clear: microserver and edge computing deployments where board space, component count, and power draw all matter. By integrating these functions, Intel reduced the external dependency of the platform while keeping the x86 instruction set that enterprise software already relied on. The result was a processor family that could serve as a complete compute-and-I/O solution in a single package, a design philosophy that set it apart from both the socketable Xeon Scalable line and the desktop-oriented Core lineup.

Answering the ARM Threat

The creation of Xeon D was not an isolated product decision; it was a direct strategic response to a shifting competitive landscape. By the mid-2010s, ARM-based hyperscale server solutions had begun gaining traction in data centers, offering what Intel perceived as superior multi-threaded throughput and power efficiency at scale. Rather than ceding that segment, Intel announced Xeon D in 2014, with silicon shipping in March 2015, specifically to counter those ARM offerings. The emphasis on lower power consumption and integrated I/O was a deliberate attempt to match the efficiency story ARM was telling while retaining the software compatibility and ecosystem depth of x86. In essence, Xeon D represented Intel's acknowledgment that the server market was fragmenting into distinct use cases, and that a one-size-fits-all high-core-count socketable chip could not address the microserver and edge niches where power budgets and board real estate were the binding constraints.

Soldered Down: The BGA Commitment

One of the most visible departures in Xeon D from the broader Xeon family is its packaging. Where mainstream Xeon processors have traditionally shipped in socketable form factors, allowing customers to swap, upgrade, or replace the CPU on a standard board, Xeon D processors are delivered exclusively in a soldered ball grid array package. This is not a minor engineering detail; it signals a different product philosophy. A soldered package is cheaper to manufacture at volume, eliminates the mechanical and electrical interface of a socket, and is well suited to high-volume, fixed-configuration deployments such as microserver blades and edge appliances where the processor is chosen once and never replaced. It also aligns with the SoC nature of the chip: if the I/O and networking are already integrated, the board design becomes a fixed, optimized unit rather than a modular platform. The BGA choice thus reinforces the idea that Xeon D is a purpose-built, cost-optimized part for specific infrastructure roles rather than a general-purpose server CPU.

From Xeon D to Xeon 6 SoC

Xeon D entered the market in March 2015 after its 2014 announcement, carving out a niche in the Intel server portfolio distinct from the high-performance Xeon Scalable line introduced in 2017 and the workstation-focused Xeon W family. For nearly a decade it occupied the microserver and edge segment as its own recognizable sub-brand. That era is now drawing to a close. In early 2025, Intel announced the Xeon 6 SoC line as the successor, at least for a portion of the Xeon D product range. This transition fits within a broader rebranding that began in April 2024 at Intel's Vision event, where the company declared it would retire the Xeon Scalable name starting with sixth-generation silicon codenamed Sierra Forest and Granite Rapids, shifting instead to a generation-numbered Xeon 6 scheme. The Xeon 6 family is further split into E-series, all efficiency-core, and P-series, all performance-core, product lines. For Xeon D customers, the move to Xeon 6 SoC signals continuity of the integrated-I/O, low-power philosophy under a new, simpler naming convention.

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