AMD Turion

Lore & Background

The Turion line began with single-core Turion 64 processors on Socket 754, featuring 512 or 1024 KiB L2 cache, a 64-bit single-channel DDR-400 memory controller, and an 800 MHz HyperTransport bus. Battery-saving PowerNow! technology was central to their marketing. Later 'Richmond' models moved to Socket S1 with a double-channel DDR2 controller. The Turion 64 X2, launched May 17, 2006 after several delays, was AMD's 64-bit dual-core mobile CPU intended to compete with Intel's Core and Core 2 CPUs. It used Socket S1, DDR2 memory, AMD Virtualization Technology, and more power-saving features. Earlier 90 nm devices were codenamed Taylor and Trinidad; newer 65 nm cores were codenamed Tyler.

The Turion X2 Ultra (codenamed Griffin) was the first processor family from AMD solely for the mobile platform, based on the Athlon 64 (K8 Revision G) architecture with enhancements similar to Phenom processors aimed at lower power consumption and longer battery life. It was released as part of the 'Puma' mobile platform in June 2008. It implemented three voltage planes (one for the northbridge and one for each core) and multiple phase-locked loops, allowing independent voltage and frequency adjustment per core. It could switch among 8 frequency levels and 5 voltage levels in microseconds, operating as low as 250 MHz. It featured deep sleep state C3, deeper sleep state C4 (AltVID), HyperTransport 3.0 up to 2.6 GHz, and multiple on-die thermal sensors. The Turion II Ultra (codenamed Caspian) was the mobile version of the K10.5 architecture on 45 nm, with clock speeds from 2.4 GHz to 2.7 GHz, 2 MB total L2 cache, HyperTransport at 3.6 GT/s, and a 128-bit FPU. The Turion II was identical except for 1 MB L2 cache and lower clock speeds.

The model naming scheme used two letters, a dash, and a two-digit number (e.g., ML-34). The first letter indicated single-core (M) or dual-core (T); the second letter indicated mobility (later in the alphabet meant more frugal power consumption). The number represented a performance rating. With the Turion II Ultra and Turion II, the methodology simplified to the letter 'M' followed by a number; higher numbers indicated higher clock speeds.

Reader's Guide

The AMD Turion line established AMD's presence in the mobile processor market, directly competing with Intel's Pentium M and Core series. Its significance lies in bringing 64-bit computing and dual-core capabilities to laptops while emphasizing power efficiency through features like PowerNow! and independent voltage planes. The Turion X2 Ultra's introduction of three voltage planes and dynamic frequency scaling allowed fine-grained power management, enabling battery life improvements. The line's evolution from 90 nm to 45 nm fabrication and from single-core to dual-core designs reflected the industry's shift toward mobile performance and efficiency. The Turion II Ultra and Turion II, based on the K10.5 architecture, maintained a 35W TDP while offering higher clock speeds and larger caches. The naming methodology, though initially opaque, was later simplified. The Turion brand ultimately demonstrated AMD's ability to deliver competitive mobile processors with architectural innovations tailored to the laptop market.

Did You Know?

• The Turion 64 X2 was launched on May 17, 2006, after several delays.
• The Turion X2 Ultra was the first AMD processor family designed solely for the mobile platform.
• The Turion II Ultra and Turion II used a simplified naming scheme with the letter 'M' followed by a number.

Architectural Lineage and Process Shrink

The Turion family traces a clear evolutionary path from the 90-nanometer Lancaster core, a single-threaded part on Socket 754 with 800 MHz HyperTransport and 512 or 1024 KiB of L2 cache, through the dual-core Taylor and Trinidad variants at 90 nm and the Tyler core at 65 nm under the Turion 64 X2 banner, to the Griffin-based Turion X2 Ultra on 65 nm SOI wafers, and finally to the Caspian-based Turion II Ultra built at 45 nm using the K10.5 architecture. A notable quirk is that the Griffin cores, despite being marketed as a new generation with enhancements similar to contemporary Phenom processors, were described by AMD Fellow Maurice Steinman as almost transistor-for-transistor identical to the 65 nm Turion 64 X2 cores. The real differentiators lay in power management and the mobile-enhanced northbridge rather than a fundamental core redesign. Memory support also evolved steadily, progressing from single-channel DDR-400 on the earliest parts to dual-channel DDR2, and eventually to DDR2-800 SO-DIMMs with a dedicated DRAM prefetcher.

Power Efficiency as Core Philosophy

From the very first Lancaster chips, battery conservation was not an afterthought but the central selling point. PowerNow! technology was baked into the earliest Socket 754 parts, and the naming scheme itself encoded power tiers: the second letter in a model designation like ML-34 versus MT-30 indicated how aggressively the chip was tuned for frugal consumption, with letters later in the alphabet denoting lower power draw. The Griffin generation pushed this philosophy further with three independent voltage planes—one for the northbridge and one per core—allowing each core to adjust its voltage and frequency independently of the other. The processor could switch among eight frequency levels and five voltage levels in a matter of microseconds, dropping as low as 250 MHz for light tasks. Deep sleep states C3 and C4 (AltVID), dynamic HyperTransport link-width scaling down to zero bits, and multiple on-die thermal sensors via an integrated SMBUS interface all served the same overriding goal: squeezing every possible watt out of a laptop battery.

Competitive Landscape and Market Positioning

AMD positioned the Turion line as its direct mobile answer to Intel's Pentium M, Core, and Core 2 processors. The single-core Turion 64 targeted the Pentium M era, while the dual-core Turion 64 X2, launched on May 17, 2006 after several delays, aimed squarely at Intel's Core and Core 2 families. The Turion X2 Ultra, released in June 2008 as part of the Puma mobile platform, and the later Turion II Ultra (Caspian, 45 nm, K10.5 architecture) continued this competitive posture. The naming convention, however, made cross-comparison difficult for consumers: a two-letter code plus a performance-rating number, such as ML-34, did not intuitively convey how one chip stacked up against another or against a desktop Athlon 64. The Turion II generation simplified this to an M prefix followed by a number indicating relative clock speed, so that an M500 at 2.2 GHz and an M520 at 2.3 GHz were straightforwardly comparable.

The Griffin Generation – Technical Pinnacle

The Turion X2 Ultra, codenamed Griffin and built on 65 nm SOI wafers, represented the most technically ambitious Turion design. Each of its two cores carried 1 MiB of L2 cache, doubling the total over the preceding Turion 64 X2. Clock speeds spanned 2.0 to 2.4 GHz at a thermal design power of 32 to 35 watts. Beyond raw specifications, Griffin introduced a mobile-enhanced northbridge integrating the memory controller, HyperTransport controller, and crossbar switch, paired with a DRAM prefetcher for DDR2-800 SO-DIMMs. HyperTransport 3.0 reached 2.6 GHz, delivering up to 41.6 GB/s per link at 16-bit width, with dynamic scaling of link width for four distinct usage scenarios. The processor also featured a MEMHOT signal from the embedded controller to reduce memory temperature, and while it reused the same Socket S1 as its predecessor, the pinout differed, requiring the RS780M chipset. Despite these platform-level innovations, the cores themselves remained K8-based rather than adopting the newer K10 microarchitecture.

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