Intel and AMD Microprocessors, Part 3 Codexery

Yonah (microprocessor)

Intel's first 65 nm mobile core, used in Core Duo and Solo.

Yonah (microprocessor)

Urbankayaker · CC BY-SA 4.0

Yonah was the code name for Intel’s first CPU cores built on a 65 nm manufacturing process, based on the earlier Banias (130 nm) and Dothan (90 nm) Pentium M microarchitecture. These cores powered Intel’s Core Solo and Core Duo mobile processors. SIMD performance got a boost from the addition of SSE3 instructions and refinements to SSE and SSE2, but integer performance took a slight hit because of higher cache latency. Yonah also included support for the NX bit.

The Intel Core Duo brand covered a dual-core microprocessor with a power draw under 25 watts, which was more power-efficient than the competing AMD Opteron 260 and 860 HE at 55 watts. It launched on January 5, 2006, as part of the Napa platform, and was the first Intel processor used in Apple Macintosh products (excluding the non-production Apple Developer Transition Kit machines, which used Pentium 4 processors).

Several variants and a derivative didn’t carry the “Intel Core” name. A dual-core server derivative, code-named Sossaman, came out on March 14, 2006, as the Xeon LV (low-voltage). It differed from Yonah only in supporting dual-socket setups (two CPUs for a total of four cores per motherboard) and 36-bit memory addressing (PAE mode). A single-core variant, Yonah-1024, was sold as the Celeron M 400 series. It was nearly identical to the Core Solo Yonah but had half the L2 cache and lacked SpeedStep and Intel VT-x. Another dual-core variant appeared as the Pentium Dual-Core T2060, T2080, and T2130 mobile CPUs, which did include Intel VT-x.

The Core Duo packed 151 million transistors, including a shared 2 MB L2 cache. Its execution core had a 12-stage pipeline, forecast to reach a maximum frequency of 2.33–2.50 GHz. Communication between the L2 cache and both cores went through a bus unit controller using arbitration, which cut down cache coherency traffic on the front side bus but raised core-to-L2 latency from 10 clock cycles (in the Dothan Pentium M) to 14 clock cycles; higher clock speeds offset the impact of that extra latency. Power management featured improved thermal control and independent power scaling between the two cores, leading to very efficient power handling. Core processors talked to the chipset over a 667 MT/s front side bus, up from 533 MT/s on the fastest Pentium M.

Quick Facts

Produced-Start
2006
Produced-End
2008
Slowest
1.06
Fastest
2.33
Slow-Unit
GHz
Fsb-Slowest
533
Fsb-Fastest
667
Fsb-Slow-Unit
MT/s
Soldby
Intel
Code
80538 (single-core) · 80539 (dual-core)
Cpuid
06Ex

Facts from the source article.

Lore & Background

Yonah was developed as part of Intel's mobile roadmap, originally focusing on reducing power consumption of the P6-based Pentium M by 50%. The resulting Core Duo offered a low-power dual-core microprocessor under 25 watts, outperforming the Mobile Pentium 4 with better power efficiency. The Yonah core included a 12-stage pipeline forecast to reach 2.33–2.50 GHz, and communication between the L2 cache and cores was handled by a bus unit controller through arbitration, raising core-to-L2 latency from 10 to 14 clock cycles but reducing cache coherency traffic over the FSB.

Several variants and derivatives existed: the dual-core server derivative Sossaman, branded as Xeon LV, supported dual-socket configurations and 36-bit memory addressing; the single-core Yonah-1024, branded as Celeron M 400 series, had half the L2 cache and lacked SpeedStep and Intel VT-x; and dual-core variants branded as Pentium Dual-Core T2060, T2080, and T2130 included Intel VT-x support. The T2300E model and certain OEM variants (T2050, T2150, T2250) dropped VT-x support, though some vendors could enable it via BIOS. Yonah did not support Intel 64 (x86-64), a limitation that became significant for its server-oriented Sossaman derivative as 64-bit operating systems grew prevalent.

Reader's Guide

Yonah represented a strategic shift for Intel, moving away from the NetBurst architecture in mobile processors toward a more power-efficient design based on the Pentium M lineage. Its dual-core implementation in the Core Duo provided performance per watt nearly as good as previous single-core Intel processors, allowing notebook computers to accomplish as much total work per battery charge as older machines, while delivering higher peak speed when parallel computations could utilize both cores. However, Yonah did not improve single-threaded processing performance over Dothan beyond SSE unit enhancements, and its 32-bit architecture proved limiting, especially for the server-oriented Sossaman derivative as x86-64 operating systems and software became increasingly prevalent. The Core Duo's inclusion of two efficient cores on one chip could outperform a Mobile Pentium 4 core with much better power efficiency. Yonah was succeeded by Intel's Core 2 processors (Merom for mobile, Conroe for desktop) on July 27, 2006, which added Intel 64 support and eventually displaced Yonah in production.

Did You Know?

The Heart of Digital Computation

A microprocessor is, at its core, a self-contained digital engine built onto a single integrated circuit or a small cluster of them. It houses the full complement of arithmetic, logic, and control circuitry that a central processing unit requires to function. Operating as a multipurpose, clock-driven, register-based device, it accepts binary data, processes that data according to instructions held in memory, and returns results in the same binary form. Both combinational and sequential digital logic work together inside the chip, enabling it to interpret and execute machine code while carrying out arithmetic operations on numbers and symbols expressed in the binary number system. In its most stripped-down conceptual form, such a processor would need nothing more than an arithmetic logic unit capable of addition, subtraction, and bitwise operations like AND or OR, paired with a control logic section that fetches opcodes from memory and orchestrates the sequence of internal operations. Each ALU operation also sets flags in a status register—signaling conditions such as zero result, negative value, or overflow—giving the processor a way to track the outcome of its most recent computation.

The Economics of Shrinking Silicon

The decision to integrate an entire central processing unit onto one or a handful of integrated circuits, made possible by very-large-scale integration techniques, fundamentally reshaped the economics of computing. Because these processors are manufactured in enormous volumes through highly automated metal-oxide-semiconductor fabrication lines, the per-unit price stays remarkably low. There is also a reliability dividend: a single-chip design simply has fewer electrical connections that can degrade or fail compared to a multi-board assembly. A principle often called Rock's law observes that as microprocessor designs grow more sophisticated, the manufacturing cost of a chip—built with smaller components on a semiconductor die of roughly the same physical size—tends to remain flat. The cumulative effect has been sweeping. Continued gains in processing capacity have pushed earlier forms of computing hardware to the point of near-total obsolescence. Today, one or more microprocessors are embedded in everything from the tiniest embedded systems and handheld gadgets to the most massive mainframes and supercomputers, a ubiquity that would have been unimaginable when computing meant filling a room with discrete circuit boards.

From Racks of Boards to a Single Die

Before the microprocessor era, even modest computers required racks of circuit boards populated with numerous medium- and small-scale integrated circuits, typically of the TTL variety. The microprocessor's defining achievement was collapsing that sprawling collection of boards into one or a few large-scale integrated circuits, consolidating what once demanded an entire cabinet of hardware into a component small enough to fit in a hand. Credit for the invention remains a matter of debate among historians and engineers, but the first microprocessor to reach commercial availability was the Intel 4004, designed by Federico Faggin and introduced in 1971. It is worth noting that the microprocessor occupies a distinct niche in the processor family. A microcontroller is a different category altogether—a system-on-chip that bundles processing with peripheral functions. A digital signal processor, meanwhile, is a specialized variant of the microprocessor whose internal architecture is tuned specifically for the operational demands of digital signal processing. Each of these devices serves a different role, yet all trace their lineage back to that foundational act of putting a CPU on a single chip.

The Physical Ceiling and the Trade-Offs

No matter how clever the design, a microprocessor's complexity is capped by hard physical limits: the maximum transistor count per die, the number of package pins connecting the chip to the system, the density of on-chip interconnections, and the heat the package can dissipate. As fabrication technology advances, each ceiling rises, making progressively more powerful processors manufacturable. This progress has allowed word sizes to climb from 4- and 8-bit figures of early designs to today's 64-bit standard, while additional on-chip registers, richer instruction sets, and integrated floating-point units have been layered into the architecture. Placing large transistor counts on one die also made it practical to embed cache memory alongside the processor, closing the growing speed gap between the ever-faster clock and comparatively sluggish external memory. Yet word size carries a cost: longer words let each clock cycle perform more computation, but they demand physically larger dies and higher standby and operating power. For that reason, 4-, 8-, or 12-bit processors remain the workhorses of embedded microcontrollers, while 16-, 32-, or 64-bit parts are chosen when a system must handle larger data volumes or more demanding interfaces.

Gallery

Frequently Asked Questions

What is Yonah in Intel's processor lineup?

Yonah is the internal code name Intel assigned to its first mobile CPU cores fabricated on a 65-nanometer process. It evolved from the Banias and Dothan designs of the Pentium M family and shipped as the silicon inside the Core Solo and Core Duo chips.

Which Intel processors were built on the Yonah core?

Yonah powered two product lines: the single-core Core Solo and the dual-core Core Duo. The Core Duo launched on January 5, 2006, and kept its total power draw under 25 watts.

How did Yonah's performance compare to the older Dothan core?

Yonah gained SIMD speed through new SSE3 instructions and refinements to existing SSE/SSE2 paths, but integer throughput dipped slightly because L2 cache latency stretched from 10 to 14 clock cycles. It also added NX-bit support, a feature Dothan lacked.

What are Yonah's key technical specifications?

The core contains 151 million transistors (including a shared 2 MB L2 cache), runs a 12-stage pipeline, and connects to the chipset over a 667 MT/s front-side bus, though some OEM variants dropped that to 533 MT/s. All of this was built on Intel's 65 nm manufacturing process.

Why is Yonah considered a milestone for Intel?

It marked Intel's first foray into 65 nm for mobile processors, proving the company could shrink its Pentium M lineage while still delivering strong battery life. The dual-core Core Duo it enabled also gave Intel a competitive edge against AMD's early mobile offerings at the time.

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