AMD Phenom

Lore & Background

The Phenom line was introduced in 2007 on the Socket AM2+ platform, using 65 nm SOI technology. The quad-core Agena processors feature four K10 cores with 512 KB L2 cache per core and a shared 2 MB L3 cache, while the triple-core Toliman models are chip-harvested from Agena dies with one core disabled. Before the original release, a flaw was discovered in the translation lookaside buffer (TLB) that could cause system lock-ups in rare circumstances. Phenom processors up to and including stepping 'B2' and 'BA' are affected by this bug. BIOS and software workarounds disable the TLB, typically incurring a performance penalty of at least 10%, which was not accounted for in pre-release previews. The 'B3' stepping, released March 27, 2008, eliminated the TLB bug and introduced 'xx50' model numbers. An AMD subsidiary released a Linux kernel patch to emulate accessed- and dirty-bits in software, causing less performance loss than previous workarounds, though the program was said in December 2007 to have received minimal functional testing.

Reader's Guide

The Phenom line marked AMD's shift from the PR rating system used in the Athlon 64 family to a four-digit model numbering scheme, with the first digit indicating the family and Energy Efficient models bearing an 'e' suffix. The TLB bug significantly impacted early adoption, as delivered performance fell short of preview benchmarks due to the workaround penalty. The B3 stepping restored expected performance and stability. The triple-core Phenom X3 series offered a mid-range option by harvesting defective quad-core dies. The Phenom line was succeeded by the upgraded Phenom II in late 2008. Its monolithic quad-core design was a notable architectural distinction from Intel's multi-chip module Core 2 Quad, though the TLB issue and delayed B3 stepping tempered its market impact.

Did You Know?

• The quad-core Phenom is considered AMD's first 'true' quad-core design because all cores are on the same silicon die.
• A TLB bug in early Phenom processors (up to B2 and BA stepping) could cause system lock-ups and required workarounds that incurred at least a 10% performance penalty.
• The B3 stepping, released March 27, 2008, fixed the TLB bug and used 'xx50' model numbers.
• Triple-core Phenom X3 processors are chip-harvested from quad-core Agena dies with one core disabled.