AMD 10h

Lore & Background

The AMD Family 10h microarchitecture, codenamed K10, succeeded the K8 family. Although AMD had not used K-nomenclature in official documents after early 2005, the name 'K8L' was coined by Charlie Demerjian in 2005 at The Inquirer and used by the IT community as shorthand. AMD officially termed it 'AMD Next Generation Processor Technology' and later 'Family 10h Processors'. The microarchitecture was also referred to as 'Stars', as desktop processor codenames were named after stars or constellations (e.g., Agena, Toliman). Giuseppe Amato confirmed in a video interview that the codename is K10. The Inquirer later revealed that 'K8L' actually referred to a low-power version of K8 (later Turion 64), and K10 was the official codename.

Key features included 128-bit wide SSE units, a 512-entry indirect branch predictor, a larger return stack, and a Side-Band Stack Optimizer. The memory subsystem gained improvements such as re-ordering loads ahead of other loads and stores, more aggressive instruction prefetching (32 bytes vs. 16 bytes in K8), a DRAM prefetcher, and buffered burst writeback. Power management was enhanced with split power planes for CPU cores and memory controller (Dynamic Independent Core Engagement, later Enhanced PowerNow!), and CoolCore technology that shuts down portions of circuits when idle.

A TLB bug in stepping B2 of Barcelona processors was discovered in November 2007, causing rare race conditions and system lockups. A BIOS or software patch worked around it by disabling cache for page tables, incurring a 5–20% performance penalty. Linux kernel patches almost completely avoided this penalty. The bug was fixed in stepping B3, released in April 2008, which also included other minor enhancements.

Reader's Guide

The AMD Family 10h (K10) microarchitecture marked a significant step in AMD's processor evolution, being the first to deliver native quad-core processors. Its launch in late 2007 directly competed with Intel's quad-core offerings, with AMD claiming performance advantages in live demonstrations. The architecture introduced several innovations that influenced later designs: split power planes for independent core and memory controller power scaling, 128-bit SSE execution units, and a more sophisticated memory subsystem with prefetching and load re-ordering. The TLB bug in early Barcelona steppings was a notable setback, requiring workarounds that impacted performance until the B3 stepping fixed it. The microarchitecture also supported multiple socket types (AM2+, AM3, FM1, Socket F) and both DDR2 and DDR3 memory, with AM3 processors offering backward compatibility. The 'K10' codename itself became a point of clarification, as the earlier 'K8L' shorthand was revealed to refer to a different product line. Overall, K10 established the foundation for AMD's subsequent Phenom and Opteron families, carrying forward the integrated memory controller design from K8 while adding native quad-core capability and enhanced power management features.

Did You Know?

• The codename 'K8L' originally referred to a low-power version of K8, later named Turion 64, not the K10 microarchitecture.
• AMD's Family 10h is the successor to Family 0Fh (K8); 10h in hexadecimal equals decimal 16.
• The TLB bug in stepping B2 of Barcelona processors could cause system lockups; a BIOS patch disabled cache for page tables, causing a 5–20% performance penalty.
• K10 processors introduced 128-bit wide SSE units and a 512-entry indirect branch predictor.