Open Core Protocol
An openly licensed, configurable on-chip interconnect protocol.
The Open Core Protocol (OCP) is a bus-independent, configurable interface for on-chip subsystem communication. It is an openly licensed, core-centric protocol, with its specifications developed by the OCP International Partnership (OCP-IP). OCP supports a range of data transfer models, from simple request-grant handshaking to pipelined request-response and complex out-of-order operations. Older legacy IP cores can be adapted to work with OCP, while new designs can select only the features and signals needed for a core's specific data, control, and test configuration. OCP is one of several interconnects used to connect soft FPGA peripherals to FPGA CPUs, including both soft microprocessors and hard-macro processors. Other similar interconnects include Advanced eXtensible Interface (AXI), Avalon, and the Wishbone bus. FPGA vendor Altera joined the OCP-IP in 2010. Advantages of OCP include eliminating the ongoing need to redefine, verify, document, and support interface protocols; readily adapting to new core capabilities; simplifying reverification through test bench portability; limiting test suite modifications when enhancing cores; interfacing with any bus structure or on-chip network; and providing industry-standard flexibility and reuse. As a point-to-point protocol, it can directly connect two cores. A notable disadvantage is that neither Altera nor Xilinx, the two largest FPGA vendors, supports this protocol.
- Producer
- OCP International Partnership (OCP-IP)
- Type
- On-chip subsystem communication protocol
- Licensing
- Openly licensed
- Data transfer models
- Simple request-grant handshaking, pipelined request-response, complex out-of-order operations
- Fpga vendor joining ocp-ip
- Altera (joined in 2010)
Lore & Background
The Open Core Protocol was developed by the OCP International Partnership to provide a standard interface for on-chip subsystem communications. It is a core-centric protocol that is bus-independent and configurable, allowing designers to select only those features and signals that encompass a core's specific data, control, and test configuration. Legacy IP cores can be adapted to OCP, while new implementations may take advantage of advanced features. OCP is one of several FPGA processor interconnects used to connect soft FPGA peripherals to FPGA CPUs—both soft microprocessors and hard-macro processors. Other such interconnects include Advanced eXtensible Interface (AXI), Avalon, and the Wishbone bus. FPGA vendor Altera joined the Open Core Protocol International Partnership in 2010.
Reader's Guide
The Open Core Protocol's significance lies in its elimination of the ongoing task of interface protocol redefinition, verification, documentation, and support. It readily adapts to support new core capabilities, and its test bench portability simplifies reverification, limiting test suite modifications for core enhancements. The protocol can interface to any bus structure or on-chip network, delivering industry-standard flexibility and reuse. As a point-to-point protocol, it can directly interface two cores. However, neither Altera nor Xilinx, the two largest FPGA vendors, supports this protocol, which limits its adoption in the broader FPGA ecosystem.
Did You Know?
- OCP data transfer models range from simple request-grant handshaking through pipelined request-response to complex out-of-order operations.
- OCP is one of several FPGA processor interconnects, alongside AXI, Avalon, and the Wishbone bus.
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