Input–output memory management unit
Maps device-visible addresses to physical memory and provides protection.
An input–output memory management unit (IOMMU) is a type of memory management unit that links a direct-memory-access–capable I/O bus to the system’s main memory. In the same way a standard MMU translates virtual addresses seen by the CPU into physical addresses, an IOMMU translates device-visible virtual addresses—often called device addresses or memory mapped I/O addresses—into physical addresses. Some IOMMUs also offer memory protection against faulty or malicious devices.
One example is the graphics address remapping table (GART) used by AGP and PCI Express graphics cards on Intel Architecture and AMD computers. On the x86 architecture, before the northbridge and southbridge functions were split between the CPU and the Platform Controller Hub (PCH), I/O virtualization was handled by the chipset rather than the CPU.
An IOMMU offers several advantages over direct physical addressing of memory via DMA. It allows large memory regions to be allocated without needing to be physically contiguous, because the IOMMU maps contiguous virtual addresses to fragmented physical ones, which can sometimes eliminate the need for vectored I/O (scatter-gather lists). Devices that cannot address the full physical memory due to address-length limits can still access all of it through the IOMMU, avoiding the overhead of copying buffers to and from the peripheral’s addressable space. For instance, x86 computers using Physical Address Extension (PAE) can address more than 4 GB of memory, but a standard 32-bit PCI device cannot access memory above the 4 GiB boundary; without an IOMMU, the operating system would need double buffering.
Memory protection is another benefit: a device cannot read or write to memory that has not been explicitly allocated to it, preventing DMA attacks from malicious devices and errant transfers from faulty ones. This protection works because the operating system running on the CPU controls both the MMU and the IOMMU exclusively, and devices cannot bypass or corrupt the configured memory management tables. In virtualization, guest operating systems can use hardware not specifically designed for virtualization, such as graphics cards that rely on DMA. Since virtual machines remap all memory addresses, DMA devices would otherwise fail; the IOMMU handles this remapping, allowing native device drivers to work inside a guest OS.
- Example implementation
- Graphics address remapping table (GART) used by AGP and PCI Express graphics cards on Intel Architecture and AMD computers
- Related specifications
- AMD-Vi, Intel VT-d, ARM SMMU, IBM TCE, PCI-SIG SR-IOV and ATS
Lore & Background
On the x86 architecture, prior to splitting the functionality of northbridge and southbridge between the CPU and Platform Controller Hub (PCH), I/O virtualization was performed by the chipset rather than the CPU. An example IOMMU is the graphics address remapping table (GART) used by AGP and PCI Express graphics cards on Intel Architecture and AMD computers. Published specifications include AMD's AMD-Vi, Intel's Virtualization Technology for Directed I/O (VT-d), and ARM's System Memory Management Unit (SMMU) to complement its virtualization architecture. IBM's Translation Control Entry (TCE) was described in a document on Logical Partition Security in the IBM eServer pSeries 690. The PCI-SIG has relevant work under Single Root I/O Virtualization (SR-IOV) and Address Translation Services (ATS).
Reader's Guide
The IOMMU provides several advantages over direct physical addressing of memory. It allows large regions of memory to be allocated without needing to be contiguous in physical memory, as the IOMMU maps contiguous virtual addresses to fragmented physical addresses, sometimes avoiding the need for vectored I/O. Devices that cannot address the entire physical memory can still access it through the IOMMU, avoiding overheads associated with copying buffers. For example, x86 computers with Physical Address Extension (PAE) can address more than 4 GB of memory, but a 32-bit PCI device cannot directly access memory above the 4 GiB boundary; without an IOMMU, the operating system would need double buffering. Memory is protected from malicious devices attempting DMA attacks and faulty devices causing errant transfers, because a device cannot read or write to memory not explicitly allocated for it. In virtualization, guest operating systems can use hardware not specifically made for virtualization; the IOMMU handles address re-mapping, allowing native device drivers to be used in a guest OS. Some architectures also use the IOMMU for hardware interrupt re-mapping. Disadvantages include performance degradation from translation and management overhead, consumption of physical memory for I/O page tables, and the need for page-aligned buffers, which may require bounce buffers and decrease performance.
Did You Know?
- An IOMMU maps device-visible virtual addresses to physical addresses, similar to how an MMU maps CPU-visible virtual addresses.
- The graphics address remapping table (GART) is an example IOMMU used by AGP and PCI Express graphics cards.
- In virtualization, the IOMMU re-maps addresses so that native device drivers can be used in a guest operating system.
- Some IOMMUs also perform hardware interrupt re-mapping in a manner similar to standard memory address re-mapping.
More in Computer Peripherals 1-24
Spotted an error? Know more?
Reader corrections go straight into our review queue. Suggest an edit · How this site is sourced