Microprocessors Codexery

IMP-16

First multi-chip 16-bit microprocessor, bit-slice design from National Semiconductor.

IMP-16

The IMP-16, released by National Semiconductor in 1973, holds the distinction of being the first multi-chip 16-bit microprocessor. Its design used five PMOS integrated circuits: four identical RALU (Register and ALU) chips handled the data path, while a single CROM (Control and ROM) chip managed control sequencing and held the microcode. As a bit-slice processor, each RALU chip contributed a 4-bit slice of the registers and arithmetic logic, working together in parallel to achieve a 16-bit word length.

Each RALU chip stored its own 4-bit portion of the program counter, several registers, the ALU, a 16-word LIFO stack, and status flags. The architecture provided four 16-bit accumulators, two of which could serve as index registers. Its instruction set closely resembled that of the Data General Nova. Like the Nova, the smallest addressable and writable memory unit was a 16-bit word, with no support for byte-level writes. The IMP-16 could address up to 64K words (128K bytes). An optional CROM II chip (IMP-16A / 522D) extended the chipset, adding 16-bit multiply and divide routines and byte operations, though byte support was limited to the lower 32K words of memory. The chipset ran on a 715 kHz four-phase non-overlapping clock with a +5 to -12 voltage swing. A key architectural feature was a 16-bit input multiplexer that supplied condition bits from the ALUs—such as zero, carry, and overflow—along with general-purpose inputs.

The microprocessor saw limited commercial use, appearing in the IMP-16P microcomputer and Jacquard Systems' J100. It was later succeeded by National Semiconductor's single-chip PACE and INS8900 16-bit microprocessors, which shared a similar architecture but were not binary compatible. Notably, the IMP-16 also found its way into the Aston Martin Lagonda, a decision influenced by National Semiconductor's chairman Peter Sprague, who was a major shareholder in Aston Martin at the time.

An example of assembler code for a subroutine called CPYMEM, which copies words from one memory location to another, demonstrates that all instructions in the basic instruction set are one word long.

Quick Facts

Numinstructions
43
Data-Width
16
Fastest
715
Fast-Unit
KHz
Successor
PACE

Facts from the source article.

Lore & Background

The IMP-16's architecture was similar to that of the Data General Nova. Each RALU chip stored its own 4 bits of the program counter, several registers, the ALU, a 16-word LIFO stack, and status flags. There were four 16-bit accumulators, two of which could be used as index registers. The smallest unit of addressable and writable memory was the 16-bit word; byte-level writes were not supported. The chipset could address up to 64K words (128K bytes). An integral part of the architecture was a 16-bit input mux that provided various condition bits from the ALUs such as zero, carry, overflow along with general purpose inputs. The chipset was driven by a 715 kHz four-phase non-overlapping clock with a +5 to -12 voltage swing.

Reader's Guide

The IMP-16 saw limited commercial use, appearing in the IMP-16P microcomputer and Jacquard Systems' J100. It was also used in the Aston Martin Lagonda, a decision influenced by National Semiconductor's chairman Peter Sprague being a major shareholder in Aston Martin at the time. The chipset could be extended with the CROM II chip (IMP-16A / 522D) that implemented 16-bit multiply and divide routines plus byte operations, though byte support was limited to the lower 32K words of memory. The IMP-16 was later superseded by the PACE and INS8900 single-chip 16-bit microprocessors, which had a similar architecture but were not binary compatible. Its bit-slice design and multi-chip approach represented an early step in 16-bit computing, though it was quickly overtaken by single-chip solutions.

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