European Processor Initiative

Lore & Background

The EPI project was divided into two phases under Specific Grant Agreements: Phase 1 (SGA1) ran from December 2018 to December 2021 under Horizon 2020, and Phase 2 (SGA2) ran from January 2022 to March 2026 under the EuroHPC Joint Undertaking. The consortium was built and selected under the Horizon 2020 Framework Partnership Agreement (FPA: 800928) and consisted of 30 institutions from 10 European countries, led by Bull in France. In 2019, the company SiPearl was incorporated to commercialize the EPI general-purpose processor (GPP) technology.

The project developed GPPs using ARM architecture and accelerators based on RISC-V ISA, targeting integration in Bull Sequana systems. Hardware design was supported by collaborative hardware/software co-design and a full-stack software ecosystem. Application target domains included automotive (Phase 1) and AI (Phase 2). The project concluded in 2026 with significant outcomes, including the demonstration of the Rhea1 chip and the EPAC test-chip family.

Reader's Guide

The European Processor Initiative's significance lies in its strategic goal of establishing European technological sovereignty in high-performance computing. By developing both general-purpose processors (ARM-based) and accelerators (RISC-V-based), EPI created a dual-pathway approach to reduce dependence on non-European technology. The project's most tangible legacy is the Rhea1 processor, featuring 80 Arm Neoverse V1 cores and over 61 billion transistors, which was selected for Jupiter, Europe's first exascale supercomputer. Its successor, Rhea2, was chosen for Alice Recoque, the second European exascale supercomputer. The EPAC accelerator test-chip family, including the Vector Processing Unit, Stencil/Tensor accelerator, and Variable Precision Unit, was silicon-proven and its IPs reused in subsequent EuroHPC projects like DARE. The project also produced hardware-related IPs (Menta Origami EDA tool, ZeroPoint DenseMem memory compression, Kalray KVX accelerators) and released the VPSim virtual prototyping simulator as open source. Several European projects (EUPILOT, EUPEX, DARE) are using EPI results to further European technology sovereignty.

Did You Know?

• SiPearl, the company formed to commercialize EPI's GPP technology, was incorporated in 2019.
• The EPAC 1.5 test chip was silicon-proven and included a Vector Processing Unit, Stencil/Tensor accelerator, and Variable Precision Unit.
• The project organized two editions of the EPI Forum (Barcelona 2024, Paris 2025) and a Codesign Workshop in Heraklion in 2025.

Strategic Mission and Two-Phase Roadmap

The European Processor Initiative was conceived as a continental-scale effort to reduce Europe's reliance on foreign silicon for its most demanding computational workloads. Its stated ambition was to design a new family of low-power microprocessors and accelerators capable of serving extreme-scale computing, high-performance computing, Big Data analytics, edge deployments, and emerging fields such as artificial intelligence and automotive systems. Beyond raw performance, the project carried a deeper geopolitical purpose: to anchor European technological autonomy and sovereignty by placing home-grown processors at the heart of future supercomputers, thereby enabling the continent to tackle societal challenges, accelerate digital transformation, and compete credibly in the global HPC market. The work was structured across two legally distinct phases. Phase 1 ran from December 2018 through December 2021 under the Horizon 2020 programme, while Phase 2, launched in January 2022 and scheduled to close in March 2026, was funded through the EuroHPC Joint Undertaking. Both phases received co-funding from the European Union, participating Member States, national Financing Authorities, and the internal budgets of the partner organisations themselves.

Architecture Choices and Industrial Ecosystem

The consortium made two pivotal architecture decisions that shaped the entire project. General-purpose processor cores were built on the ARM instruction set, while the accelerator line adopted the open RISC-V ISA. Both were intended for integration into Bull Sequana supercomputer systems. To give the technology a commercial path, a dedicated company called SiPearl was incorporated in 2019, serving as the industrial arm tasked with bringing the general-purpose processor technology to market. A defining methodological choice was the emphasis on collaborative hardware-software co-design. Rather than treating silicon and software as separate workstreams, the team developed a comprehensive full-stack software ecosystem alongside the hardware, ensuring that both the general-purpose cores and the accelerators would be supported end-to-end. Validation was grounded in real workloads: flagship scientific applications were used to exercise the designs, and specific target domains were selected for each phase—automotive in Phase 1 and artificial intelligence in Phase 2—so that the new architectures could be stress-tested against application requirements that both benefited from and informed the architectural choices.

Silicon Proofs and Exascale Selections

By the close of Phase 2 in 2026, the project had produced tangible silicon results. SiPearl showed the Rhea1 chip executing a full high-performance computing software stack on a test board. The system booted a standard Linux distribution, interfaced with high-bandwidth memory and its associated performance monitoring counters, and successfully ran both the HPL and STREAM benchmarks—evidence that the complete Rhea1 ecosystem was ready for exascale workloads. The chip packs 80 ARM Neoverse V1 cores, over 61 billion transistors, four stacks of built-in HBM, four DDR5 interfaces, and 104 lanes of PCIe Gen5 connectivity. Jupiter, Europe's first exascale supercomputer, was chosen to implement Rhea1, while its successor, Rhea2, was selected for Alice Recoque, the continent's second exascale machine. In parallel, the EPAC test-chip family gathered a Vector Processing Unit led by SemiDynamics and BSC, a Stencil/Tensor accelerator led by Fraunhofer, and a Variable Precision Unit led by CEA. The EPAC 1.5 test chip reached silicon, and the VEC accelerator was mapped onto a multi-FPGA system built on the MEEP infrastructure.

Consortium Structure and Enduring Legacy

EPI was not a single company's project but a broad European collaboration. The consortium, selected under the Horizon 2020 programme's ICT-42-2017 call, brought together 30 institutions spanning 10 European countries, with France's Bull serving as the coordinating lead. The group included companies, universities, and research organisations, and it operated as a non-legal entity rather than a formal corporate structure. Throughout its life, the consortium organised and participated in numerous community events. The most prominent were two editions of the EPI Forum—held in Barcelona in 2024 and Paris in 2025—and the EPI Codesign Workshop in Heraklion in 2025. The project's influence extends well beyond its 2026 conclusion. Several European follow-on projects, including EUPILOT, EUPEX, and DARE, are building directly on EPI's results to advance the continent's push toward technology sovereignty. Additional hardware-related intellectual property developed during the project—such as the Menta Origami EDA tool, ZeroPoint DenseMem memory compression, and Kalray KVX accelerators—did not reach silicon but remain available for reuse. CEA-List also released VPSim, a virtual prototyping simulator, as open source for early software-hardware co-validation and performance exploration.