Tick–tock model
Intel's alternating die-shrink and new-architecture production cycle.
Intel introduced the tick–tock production model in 2007. In this approach, each new manufacturing process debuted with a die shrink of an existing microarchitecture—called a "tick"—followed by a completely new microarchitecture built on that now-stable process—called a "tock." The cycle repeated roughly every 12 to 18 months. More broadly, tick–tock describes an engineering pattern where one half of a two-part system is refreshed per release cycle.
The model ended in 2016, when Intel announced a shift to a process–architecture–optimization model. This three-step cycle works like a tick–tock sequence but adds an optimization phase after the tock. The change came because process improvements were slowing. In 2014, Intel had already introduced a "tock refresh"—a minor update to a tock microarchitecture that wasn't considered a full new generation. The company stated in a March 2016 Form 10-K that it would make such refreshes standard going forward.
Under the new model, three processor generations are produced on the same manufacturing process. For example, after launching the Skylake architecture on 14 nm in 2015, the first optimization was Kaby Lake in 2016, followed by a second optimization, Coffee Lake, in 2017. This meant four generations at 14 nm before the Palm Cove die shrink to 10 nm in 2018.
Intel attempted to apply tick–tock to its Atom architecture starting with Silvermont, but problems with the 10 nm process prevented it. The Atom roadmap now uses the process–architecture–optimization model in tables, though Intel has not officially confirmed this for Atom. The Xeon Phi line went through four development steps, with its top model, Knights Landing, derived from the Silvermont architecture but built on a shrunk 14 nm FinFET process. Intel discontinued all Xeon Phi CPUs in 2018, though later Atom-based Xeon CPUs like Sierra Forest are considered a spiritual successor.
- Adopted
- 2007
- Replaced by
- process–architecture–optimization model (announced 2016)
- Cycle length
- roughly every year to 18 months
- Tick definition
- shrinking of process technology of previous microarchitecture (with minor changes, commonly to caches, rarely introducing new instructions)
- Tock definition
- new microarchitecture
- Tock refresh introduced
- 2014
- Process architecture optimization steps
- three generations under a single manufacturing process
Lore & Background
Every 'tick' represented a shrinking of the process technology of the previous microarchitecture, with minor changes commonly to the caches and rarely introducing new instructions, as with Broadwell in late 2014. Every 'tock' designated a new microarchitecture. These occurred roughly every year to 18 months. Due to the slowing rate of process improvements, in 2014 Intel created a 'tock refresh' of a tock in the form of a smaller update to the microarchitecture not considered a new generation in and of itself. In March 2016, Intel announced in a Form 10-K report that it would always do this in future, deprecating the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization. After introducing the Skylake architecture on a 14 nm process in 2015, its first optimization was Kaby Lake in 2016. Intel then announced a second optimization, Coffee Lake, in 2017 making a total of four generations at 14 nm before the Palm Cove die shrink to 10 nm in 2018. With Silvermont Intel tried to start tick-tock in Atom architecture but problems with the 10 nm process prevented it. In the table for Atom, process-architecture-optimization steps are used instead of tick-tock; there is no official confirmation that Intel uses process-architecture-optimization for Atom, but it enables understanding of what changes happened in each generation.
Reader's Guide
The tick–tock model was notable for structuring Intel's processor development into predictable alternating phases of process shrinkage and architectural innovation, enabling roughly annual or 18-month product cadences. Its significance lies in how it disciplined Intel's engineering roadmap for nearly a decade, from 2007 until its deprecation in 2016. The model's eventual replacement by the process–architecture–optimization model reflected the slowing rate of process improvements, as Intel found it necessary to insert an optimization phase between architectural generations. This shift allowed three generations of processors under a single manufacturing process, as seen with the 14 nm node which produced Skylake, Kaby Lake, and Coffee Lake before the 10 nm Palm Cove die shrink. The model also influenced Intel's Atom line, though problems with the 10 nm process prevented a full tick-tock implementation there. The Xeon Phi line, derived from the Silvermont architecture used in Atom, underwent four development steps with its top model code-named Knights Landing, but was discontinued in 2018; Sierra Forest and subsequent Atom-based Xeon CPUs are considered a likely spiritual successor. The tick–tock model's legacy includes its role in establishing a rhythm for semiconductor development that later had to adapt to physical and economic constraints.
Did You Know?
- Tick–tock was adopted by Intel in 2007.
- The model was replaced by the process–architecture–optimization model announced in March 2016.
- Intel created a 'tock refresh' in 2014 due to slowing process improvements.
More in Intel and AMD Microprocessors, Part 2 1-24
Spotted an error? Know more?
Reader corrections go straight into our review queue. Suggest an edit · How this site is sourced