Goldmont
Second-generation out-of-order low-power Atom microarchitecture for entry-level devices.
Goldmont is a 14 nm microarchitecture from Intel, used in low-power Atom, Celeron, and Pentium processors built as systems on a chip (SoCs). Each core supports only a single thread. The architecture debuted in April 2016 at the Intel Developer Forum in Shenzhen, China, as part of the Apollo Lake platform. It draws heavily from the Skylake Core architecture, delivering a performance increase of over 30% compared to the earlier Braswell platform. Goldmont targets power-efficient, entry-level devices such as Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.
Goldmont is Intel’s second-generation out-of-order low-power Atom microarchitecture, designed for basic desktop and notebook computers. It uses a 14 nm process and supports up to four cores in consumer devices. Graphics are handled by the Intel Gen9 architecture, first introduced with Skylake.
Building on the Silvermont microarchitecture, Goldmont includes several enhancements. Its out-of-order execution engine features a 3-wide superscalar pipeline: the decoder can process three instructions per cycle, the microcode sequencer can send three μops per cycle for allocation into reservation stations, and retirement can handle up to three operations per cycle. Branch prediction has been improved by decoupling the fetch pipeline from the instruction decoder. The out-of-order execution window and buffers are larger, allowing deeper out-of-order execution across integer, floating-point/SIMD, and memory instruction types. Memory execution is fully out-of-order with disambiguation, enabling one load and one store per cycle (compared to one load or one store per cycle in Silvermont). The memory pipeline also includes a second-level TLB with 512 entries for 4 KB pages.
The integer execution cluster provides three pipelines, capable of executing up to three simple integer ALU operations per cycle. SIMD integer and floating-point instructions run in a 128-bit wide engine, with improved throughput and latency for many instructions—for example, PSHUFB achieves 1-cycle throughput versus 5 cycles in Silvermont, and many other SIMD instructions have doubled throughput. Instructions for accelerating AES encryption/decryption and carry-less multiplication (PCLMULQDQ) have also been significantly improved.
Quick Facts
- Cores
- 2–4
- Code
- 80668 (Apollo Lake) · 80765 (Denverton)
- Instructions
- x86-64, Intel 64
- Extensions
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- Predecessor
- Airmont (die shrink)
- Successor
- Goldmont Plus (optimization)
Facts from the source article.
Lore & Background
Goldmont builds on the success of the Silvermont microarchitecture and provides a 3-wide superscalar pipeline with out-of-order execution. The decoder can decode three instructions per cycle, the microcode sequencer can send three μops per cycle for allocation into reservation stations, and retirement supports a peak rate of three per cycle. Branch prediction is enhanced by decoupling the fetch pipeline from the instruction decoder, and the larger out-of-order execution window and buffers enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types. The memory execution pipeline is fully out-of-order with disambiguation, executing one load and one store per cycle, and includes a second-level TLB enhancement with 512 entries for 4 KB pages. The integer execution cluster provides three pipelines and can execute up to three simple integer ALU operations per cycle. SIMD integer and floating-point instructions execute in a 128-bit wide engine, with improved throughput and latency for many instructions, including PSHUFB achieving 1-cycle throughput versus 5 cycles in Silvermont. Throughput and latency for AES encryption/decryption and PCLMULQDQ carry-less multiplication have been significantly improved, and new instructions for hardware-accelerated secure hashing (SHA1 and SHA256) are added. The RDSEED instruction for random number generation meeting NIST SP800-90C standard is also supported, and the PAUSE instruction latency is optimized for better power efficiency.
Reader's Guide
Goldmont's significance lies in its role as the second-generation out-of-order low-power Atom microarchitecture, delivering a substantial performance increase over its predecessor while maintaining low power consumption suitable for a wide range of entry-level and embedded devices. By borrowing heavily from the Skylake Core architecture, it brought advanced features such as Gen9 graphics, hardware-accelerated security and hashing instructions, and improved SIMD performance to the low-power segment. The Apollo Lake platform enabled devices like Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems. However, the architecture was affected by a design flaw documented as erratum APL46, which could cause systems to cease operation after several years of active use due to degradation of LPC, RTC, SD card, and GPIO interfaces. Mitigations included firmware updates and usage restrictions, though some systems were incompatible with the fixes. The legacy of Goldmont includes its influence on subsequent low-power Intel designs, with newer architectures such as Atom C3000 Denverton not appearing to be affected by the same erratum.
Did You Know?
- Goldmont allows only one thread per core.
- The architecture supports up to four cores for consumer devices.
- It includes the Intel Gen9 graphics architecture introduced with Skylake.
- An erratum named APL46 documented that LPC, RTC, SD card, and GPIO interfaces may stop functioning after several years of active use.
Frequently Asked Questions
What is Goldmont?
Goldmont is Intel's 14 nm, second-generation out-of-order microarchitecture built exclusively for low-power Atom, Celeron, and Pentium SoCs. Each core handles a single thread, and the design debuted in April 2016 as part of the Apollo Lake platform.
How does Goldmont relate to Skylake?
Intel derived much of Goldmont's internal design from the Skylake Core microarchitecture, then stripped it down to a simpler, single-thread-per-core layout suited to ultra-low-power parts. That Skylake heritage is largely what drove the 30%+ performance gain over the prior Braswell generation.
What kinds of products actually use Goldmont?
You'll find Goldmont-based chips in Cloudbooks, 2-in-1 netbooks, small-form-factor PCs, IP cameras, and in-car entertainment systems. It targets the entry-level and embedded segment where a single-digit-watt envelope matters more than raw multi-thread throughput.
What are Goldmont's headline specifications?
Consumer parts top out at four cores with a 10 W TDP on desktop/server boards, while mobile variants run at 4–6 W. The instruction set covers SSE4.2, AES-NI, PCLMUL, RDRAND, RDSEED, Intel SHA extensions, and MPX, and the integrated GPU uses Intel's Gen9 graphics architecture.
Why is Goldmont important in Intel's processor history?
It gave Intel a credible performance step-up for budget and embedded customers without requiring full Core-class silicon. By pairing a Skylake-derived pipeline with a strict single-thread, low-watt design, Intel could serve a massive volume of entry-level devices that had previously been stuck on older, less efficient architectures.
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