Tejas and Jayhawk

Lore & Background

In early 2003, Intel showed Tejas and planned a release in 2004 with possible delays into 2005. Development was cancelled on May 7, 2004. Analysts attributed the cancellation to heat and power consumption problems stemming from Intel's pursuit of ever-higher clock speeds at the expense of work done per clock. This issue had already surfaced with Prescott, which showed mediocre performance increases over Northwood despite higher clocks, and faced heavy competition from AMD's Athlon 64. Prescott was supposed to reach over 5 GHz easily but could not due to physical limitations of heat and power at ambient temperatures—the 'power wall.' Tejas pushed further, with Intel targeting 10 GHz by 2011 to fulfill a prediction made by Andrew Grove at the 1996 COMDEX/Fall, but this proved a dead end.

Tejas and Jayhawk were to improve on the NetBurst microarchitecture. The trace cache capacity would likely have been increased, and the number of pipeline stages was increased to between 40 and 50. An improved version of Hyper-Threading and a new SSE version (later backported to Core 2 as SSSE3) were planned. Tejas was slated to operate at frequencies of 7 GHz or higher, though it likely would have executed fewer instructions per clock due to more pipeline bubbles from branch mispredicts and data cache misses. It would have run hotter, with a TDP much higher than Prescott. The CPU was cancelled late in development after reaching its tapeout phase. Initial claims reported early samples of single-core 90 nm Tejas running at 2.8 GHz and rated for 150 W TDP on LGA 775, a notable increase over Prescott (84 W) and higher than dual-core Smithfield (95 W). However, the existence of engineering samples has been challenged, and no source indicates that tape-out of Tejas ever existed—the sample shown in an article being a Prescott B0 ES. Most probably only thermal samples of Tejas were produced.

Reader's Guide

The cancellation of Tejas and Jayhawk reflected Intel's intention to focus on dual-core chips for the Itanium platform and, for desktops, to shift development to the Pentium M microarchitecture (derived from the P6 microarchitecture used in the Pentium III). The Pentium M, used in the Centrino notebook platform, offered greatly improved performance per watt compared to Prescott and other NetBurst designs. Modernizing the P6 microarchitecture led to the Core processor line and later the Core 2 line, which provided Intel's first native dual-core products for desktops and laptops and regained the performance crown from AMD. This defined the end of the NetBurst architecture, with Core setting the foundation for power-efficient architectures that followed along the Tick–tock model. Although NetBurst was a dead end, its concepts were later reused and repurposed in Sandy Bridge. To bridge the gap left by Tejas' cancellation in the x86 market, Intel did one last revision to NetBurst, code-named Cedar Mill (single core) and Presler (dual core).

Did You Know?

• Tejas was sometimes referred to as Pentium V.
• The processor was cancelled on May 7, 2004, after reaching its tapeout phase.
• Intel targeted 10 GHz clock speeds by 2011 with the Tejas paradigm.
• A dual-core version of Tejas was code-named Cedarmill (or Cedar Mill), but the codename was later recycled for a 65 nm Pentium 4.