Second Level Address Translation

Lore & Background

The need for SLAT arose from the overhead of double address translation in virtual machines. In a virtualized system, a guest operating system performs its own virtual-to-physical address translation, and the host must then translate those guest-physical addresses to host-physical addresses. Software-based shadow page tables reduce this to a single translation but require the hypervisor to manage updates whenever the guest modifies its page tables, incurring significant cost.

AMD introduced Rapid Virtualization Indexing (RVI) with its third-generation Opteron processors (Barcelona). Intel followed with Extended Page Tables (EPT) in the Nehalem microarchitecture, found in certain Core i7, Core i5, and Core i3 processors. ARM's virtualization extensions provide Stage-2 page-tables via a Stage-2 MMU, with the guest using the Stage-1 MMU; support was added as optional in ARMv7ve and is also present in ARMv8 architectures.

Mode Based Execution Control (MBEC) extends x86 SLAT by splitting the execute bit into two bits—one for user execute and one for supervisor execute. This allows sharing a single page table between unsigned usermode code and signed kernelmode code, eliminating VM exits on context switches between the two modes. MBEC first appeared in Intel Kaby Lake and AMD Zen 2 CPUs (called Guest Mode Execute Trap on AMD).

Reader's Guide

SLAT significantly improves virtualization performance by offloading address translation to hardware, reducing the overhead of shadow page table management. VMware research reported up to 42% performance gains with RVI over software-only implementations, and up to 48% for MMU-intensive benchmarks with EPT, with microbenchmarks showing up to 600% improvement. However, EPT can cause code to run slower than a software implementation in some corner cases.

The technology is foundational for modern hypervisors. Many hypervisors require SLAT to function at all, as they do not implement software shadow page tables. Examples include Hyper-V on Windows 8 and later, VMware Workstation 14 and later, Qubes OS, bhyve, and OpenBSD's vmm. Other hypervisors such as KVM, Xen, VirtualBox, and Parallels Desktop support SLAT for performance gains. The use of large pages in host page tables (e.g., 2 MB pages in x86-64) reduces the depth of look-ups and memory required, an obvious optimization since memory is typically allocated to virtual machines at coarse granularity.

Did You Know?

• SLAT is also known as nested paging.
• AMD's implementation is called Rapid Virtualization Indexing (RVI), originally developed as Nested Page Tables (NPT).
• Intel's Extended Page Tables (EPT) are required for the 'unrestricted guest' feature that allows launching a logical processor directly in real mode.
• ARM's Stage-2 page-tables are provided by a Stage-2 MMU, while the guest uses the Stage-1 MMU.