Sandy Bridge
Intel's 2011 32 nm microarchitecture succeeding Nehalem and Westmere.
Sandy Bridge is a CPU microarchitecture from Intel, built on a 32 nm manufacturing process and released in 2011. It served as the "tock" in Intel's Tick–tock model, following Nehalem and Westmere. Processors based on Sandy Bridge are sold as the second generation Core lineup, along with various Xeon, Pentium, and Celeron models. Intel first showed an A1 stepping Sandy Bridge processor at the Intel Developer Forum in 2009, and the first products hit the market in January 2011.
These processors use a soldered connection between the die and the integrated heat spreader. Production of Sandy Bridge family chips continued until September 27, 2013 for desktop and mobile units, November 24, 2013 for workstation, high-end desktop, and server units, and through the end of 2015 for embedded devices.
Key upgrades over Nehalem include Intel Turbo Boost 2.0, 32 KB data and 32 KB instruction L1 cache plus 256 KB L2 cache per core, and a shared L3 cache that includes the processor graphics on LGA 1155 sockets. The cache line size is 64 bytes. A new micro-operation cache holds up to 1,536 entries. Each core has three integer ALUs, two vector ALUs, and two AGUs. Two load/store operations per CPU cycle are possible per memory channel. The architecture features a decoded micro-operation cache and an enlarged, optimized branch predictor. Sandy Bridge keeps Nehalem's four branch predictors: the branch target buffer (BTB), indirect branch target array, loop detector, and renamed return stack buffer (RSB). It uses a single BTB that holds twice as many branch targets as Nehalem's L1 and L2 BTBs combined. Performance improvements also cover transcendental mathematics, AES encryption via the AES instruction set, and SHA-1 hashing. A 256-bit/cycle ring bus connects cores, graphics, cache, and the System Agent Domain. The architecture supports Advanced Vector Extensions (AVX) with 256-bit instructions, wider vectors, and new syntax. Up to eight physical cores or sixteen logical cores through hyper-threading are available, starting from six cores and twelve threads. The GMCH (integrated graphics and memory controller) and processor are integrated into a single die within the package, unlike the predecessor Clarkdale which used two separate dies. This reduces memory latency further.
Quick Facts
- Produced-Start
- 2011-01-09
- Produced-End
- 2013-09-27 (mobile and desktop units) / 2013-11-24 (workstations and servers) / 2015-12-27 (embedded devices)
- Model
- Celeron / Pentium / Core i3/i5/i7/i7 Extreme / Xeon E3/E5
- Cores
- 1–4 (4-6 Extreme, 2-8 Xeon) / <!-- (2–8)
- Code
- 80619 (extreme desktop) / 80620 (server LGA1356) / 80621 (server LGA2011) / 80623 (desktop) / 80627 (mobile)
- Transistors
- 504M to 2.27B 32nm / <!-- (Q0)
- Slowest
- 1.60
- Fastest
- 3.60
Facts from the source article.
Lore & Background
Sandy Bridge-based processors use soldered contact between the die and integrated heat spreader (IHS). Its 22 nm successor, Ivy Bridge, uses only thermal interface material (TIM) instead. The Sandy Bridge family was produced up until September 27, 2013 for desktop and mobile units, November 24, 2013 for workstation, high-end desktop and server units, and the end of 2015 for embedded devices.
Upgraded features from Nehalem include Intel Turbo Boost 2.0, a new μOP cache up to 1536-entry, improved integer and vector ALUs, and a 256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain. Sandy Bridge integrates the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package, reducing memory latency. It also introduced Advanced Vector Extensions (AVX) 256-bit instruction set.
On 31 January 2011, Intel issued a recall on all 67-series motherboards due to a flaw in the Cougar Point Chipset. A hardware problem existed in which the chipset's SATA II ports could fail over time. Intel stopped production of flawed B2 stepping chipsets and began producing B3 stepping chipsets with the silicon fix. Sandy Bridge processor sales were temporarily on hold, as one cannot use the CPU without a motherboard.
Reader's Guide
Sandy Bridge represented a significant integration milestone, combining the processor, memory controller, and integrated graphics onto a single die, which reduced memory latency and improved performance. The average performance increase at clock to clock was 11.3% compared to the Nehalem generation, with roughly twice the integrated graphics performance compared to Clarkdale. Intel tied the speed of every bus to a single internal clock generator (BClk), limiting overclocking on multiplier-locked CPUs to a 5–7% BClk increase; K/X-series processors with unlocked multipliers were made available as a workaround, with a multiplier cap of 57 for Sandy Bridge. The architecture introduced Intel Quick Sync Video for hardware video encoding/decoding, and the Intel Data Plane Development Kit (Intel DPDK) for communications applications. Sandy Bridge and Ivy Bridge processors also contained a DRM technology called Intel Insider that some video streaming sites relied on for 1080p streaming. The architecture's lifespan extended into 2015 for embedded devices, and its successor, Ivy Bridge, was released on a 22 nm process.
Did You Know?
- Sandy Bridge processors use soldered contact between the die and integrated heat spreader, while Ivy Bridge uses thermal interface material.
- Intel demonstrated an A1 stepping Sandy Bridge processor in 2009 during Intel Developer Forum.
- The Cougar Point chipset flaw caused a recall of all 67-series motherboards in January 2011.
More in Intel and AMD Microprocessors, Part 2 1-24
Spotted an error? Know more?
Reader corrections go straight into our review queue. Suggest an edit · How this site is sourced