Pentium Pro
First x86 processor with out-of-order execution and P6 microarchitecture.
The Pentium Pro, launched by Intel on November 1, 1995, was the company’s first sixth-generation x86 processor and the first to use the P6 microarchitecture (also called i686), which replaced the P5 design found in the original Pentium. While the original Pentium and Pentium MMX had 3.1 and 4.5 million transistors respectively, the Pentium Pro packed 5.5 million. It supported both dual- and quad-processor setups and came exclusively in the large rectangular Socket 8 form factor.
Intel initially planned for the Pentium Pro to take over from the original Pentium across all applications, but later scaled back its role to servers and high-end desktops. It eventually found a place in supercomputers, most notably ASCI Red in 1996, which became the first computer to exceed one teraFLOPS and held the top spot on the TOP500 list from 1997 to 2000. ASCI Red used dual-processor nodes, each with two Pentium Pro CPUs. The Pentium Pro was succeeded in 1998 by the Pentium II Xeon, also based on the P6 architecture.
The chip’s lead architect was Fred Pollack, a specialist in superscalar design who had previously led work on the Intel iAPX 432. The Pentium Pro introduced a decoupled, 14-stage superpipelined architecture that relied on an instruction pool. Its pipeline included extra decode stages that dynamically translated IA-32 instructions into buffered micro-operation sequences. These micro-ops could be analyzed, reordered, and renamed to find parallelizable operations for multiple execution units, enabling out-of-order and speculative execution via register renaming. A wider 36-bit address bus, usable with Physical Address Extension (PAE), allowed access to up to 64 GB of memory.
The processor had an 8 KB instruction cache, fetching up to 16 bytes per cycle for three instruction decoders. Only one decoder could handle any x86 instruction; the other two were limited to simple ones, which constrained simultaneous decoding and superscalar performance. Instructions were decoded into 118-bit micro-ops, RISC-like in structure (encoding an operation, two sources, and a destination). The general decoder could produce up to four micro-ops per cycle, while each simple decoder produced one. Instructions operating on memory required at least three micro-ops and could only be handled by the general decoder.
Quick Facts
- Produced-Start
- 1995-11-01
- Produced-End
- 1998
- Slowest
- 150
- Slow-Unit
- MHz
- Fastest
- 200
- Fsb-Slowest
- 60
- Fsb-Slow-Unit
- MT/s
- Fsb-Fastest
- 66
- Arch
- x86
- Microarch
- P6
Facts from the source article.
Lore & Background
The Pentium Pro incorporated a decoupled, 14-stage superpipelined architecture using an instruction pool. It featured out-of-order execution, speculative execution via register renaming, and a wider 36-bit address bus usable by Physical Address Extension (PAE), allowing access to up to 64 GB of memory. The lead architect was Fred Pollack, who specialized in superscalarity and had worked as lead engineer of the Intel iAPX 432. The processor had an 8 KB instruction cache, three instruction decoders (one general, two simple), and translated x86 instructions into 118-bit micro-operations. It was the first x86 family processor to support upgradeable microcode under BIOS and/or operating system control. A bug was discovered in the floating point unit, called the 'Pentium Pro and Pentium II FPU bug' or 'flag erratum', occurring during floating point-to-integer conversion when the number would not fit into the smaller integer format. The Pentium Pro was capable of dual- and quad-processor configurations and only came in the Socket 8 form factor.
Reader's Guide
The Pentium Pro's P6 microarchitecture was used in one form or another by Intel for more than a decade, scaling from its initial 150 MHz start up to 1.4 GHz with the 'Tualatin' Pentium III. Its design traits continued in the derivative core called 'Banias' in Pentium M and Intel Core (Yonah), which evolved into the Core microarchitecture (Core 2 processor) in 2006 and onward. Despite being advanced, its out-of-order register renaming architecture had trouble running 16-bit code and mixed code, causing frequent pipeline flushing. This, along with high cost, led to tepid sales among PC buyers at the time. To fully use the P6 microarchitecture, a fully 32-bit operating system was needed, such as Windows NT, Linux, Unix, or OS/2. The Pentium Pro introduced conditional move instructions (CMOVcc and FCMOVcc) and documented the UD2 illegal instruction. Its successor was the Pentium II Xeon in 1998, also derived from P6.
Did You Know?
- The Pentium Pro was the first x86-based Intel processor to implement the P6 microarchitecture.
- It was used in the ASCI Red supercomputer, the first computer to reach over one teraFLOPS.
- The Pentium Pro had 5.5 million transistors, compared to 3.1 million in the original Pentium and 4.5 million in the Pentium MMX.
- It introduced conditional move instructions (CMOVcc and FCMOVcc) into the Intel range.
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