Penryn (microarchitecture)
45-nm die shrink of Core microarchitecture with SSE4.1 and larger cache.
Penryn is the code name for the 45-nanometer shrink of the Core microarchitecture, which served as the "Tick" in Intel's Tick-Tock model. It appears in Core 2 processors under the names Penryn (Socket P), Wolfdale (LGA 775), and Yorkfield (a multi-chip module for LGA 775). Some of these chips are also marketed as Celeron, Pentium, or Xeon processors. On the Xeon side, the Wolfdale-DP and Harpertown names refer to LGA 771 multi-chip modules that contain either two or four active Wolfdale cores.
Architecturally, the 45-nanometer Core 2 CPUs improved on the 65-nanometer versions with a faster divider (lower latency), a new shuffle engine, and support for SSE4.1 instructions—some of which rely on that single-cycle shuffle engine. The maximum L2 cache per chip grew from 4 MB to 6 MB, and its associativity increased from 16-way to 24-way. There are also cut-down versions with 3 MB L2, commonly called Penryn-3M, Wolfdale-3M, or Yorkfield-6M. The single-core variant, Penryn-L, is not a separate design like Merom-L; it is simply a Penryn-3M die with only one active core.
Processors in this family are grouped by core count, cache size, and socket, each combination having a unique code name and product code used across multiple brands. For example, the code name "Allendale" (product code 80557) has two cores, 2 MB L2, and a desktop LGA 775 socket, but it has been sold as Celeron, Pentium, Core 2, and Xeon with different feature sets enabled. Most mobile and desktop versions come in two L2 cache sizes, though the actual amount can also be reduced by disabling parts during manufacturing.
Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules that combine two dies. For the 65 nm processors, the same product code might cover different dies, but the specific die can be identified by the stepping.
For the 45 nm process, Intel began selling steppings with full (6 MB) and reduced (3 MB) L2 cache at the same time, both sharing identical CPUID values. All steppings include SSE4.1. Stepping C1/M1 was a bug-fix of C0/M0, used only in quad-core processors. Stepping E0/R0 added two new instructions (XSAVE/XRSTOR) and replaced all earlier steppings. In mobile processors, C0/M0 only works with the Intel Mobile 965 Express (Santa Rosa refresh) platform, while E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.
Quick Facts
- Created
- November 2007
- Model
- P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon) / <!-- Celeron Series
- Cores
- 1-4 (2-6 Xeon) / <!--
- Transistors
- 228M to 820M 45 nm / <!-- (R0)
Facts from the source article.
Lore & Background
Penryn was the 2007/2008 'Tick' die shrink of the Core microarchitecture to 45 nanometers, carrying CPUID model 23. Architectural improvements over the 65-nanometer Core 2 CPUs include a new divider with reduced latency, a new shuffle engine, and SSE4.1 instructions, some of which are enabled by the new single-cycle shuffle engine. Maximum L2 cache size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way; cut-down versions with 3 MB L2 also exist, commonly called Penryn-3M, Wolfdale-3M, and Yorkfield-6M. The single-core version, Penryn-L, is not a separate model but a version of Penryn-3M with only one active core.
In the model 23 family, Intel started marketing steppings with full (6 MB) and reduced (3 MB) L2 cache at the same time, giving them identical cpuid values. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad-core processors. Stepping E0/R0 added two new instructions (XSAVE/XRSTOR) and replaced all earlier steppings. In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.
Model 29 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, leading to an unusually large die size of 503 mm². As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington). Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies.
Reader's Guide
Penryn's significance lies in its role as the 45-nanometer 'Tick' in Intel's Tick-Tock cycle, delivering a die shrink of the Core microarchitecture that improved performance per watt and enabled higher clock speeds. The architectural enhancements—such as the reduced-latency divider, single-cycle shuffle engine, and SSE4.1 instructions—provided tangible benefits for multimedia and computational workloads. The increase in L2 cache from 4 MB to 6 MB with 24-way associativity improved data throughput, while the introduction of cut-down 3 MB variants allowed Intel to address different market segments from the same die design. The multi-chip module approach for quad-core processors (Yorkfield, Harpertown) and the later addition of L3 cache in the six-core Dunnington (Xeon 7400 series) demonstrated Intel's ability to scale the architecture upward. The stepping evolution, particularly the E0/R0 revision adding XSAVE/XRSTOR instructions, shows ongoing refinement. Penryn's legacy is as a transitional but highly successful microarchitecture that bridged the 65-nm Core 2 era to the Nehalem-based 'Tock' that followed, and its derivatives served in mobile, desktop, and server platforms across multiple brands including Celeron, Pentium, Core 2, and Xeon.
Did You Know?
- Maximum L2 cache per chip increased from 4 MB to 6 MB with 24-way associativity.
- Stepping E0/R0 added XSAVE/XRSTOR instructions and replaced all earlier steppings.
- The six-core Dunnington (Xeon 7400 series) has a die size of 503 mm² and includes an L3 cache.
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