P6 (microarchitecture)

Lore & Background

The P6 core was the sixth generation Intel microprocessor in the x86 line, succeeding the original Pentium design (P5). It was partially succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, though it continued to be used in new processors through the mid-2000s. The Core microarchitecture, an evolution of the Enhanced Pentium M variant of P6 with 64-bit, XD bit and SSE3 implementation, would later succeed both P6 and NetBurst.

Features first implemented in the x86 space in the P6 core include speculative execution and out-of-order execution (called 'dynamic execution' by Intel), superpipelining (increasing from Pentium's 5-stage pipeline to 14 stages), a front-side bus using a variant of Gunning transceiver logic, Physical Address Extension (PAE) with a 36-bit address bus, register renaming, and CMOV instructions. The Pentium M variant modernized the design with a quad-pumped front-side bus, larger L1/L2 cache, SSE2 support, an overhauled branch predictor, and micro-operation fusion.

The Yonah CPU, launched in January 2006 under the Core brand, provided partial solutions to some of the Pentium M's shortcomings by adding SSE3 support, single- and dual-core technology with 2 MB of shared L2 cache, increased FSB speed, and a 12-stage instruction pipeline. This resulted in an interim microarchitecture for low-voltage CPUs, part way between P6 and the following Core microarchitecture.

Reader's Guide

The P6 microarchitecture's significance lies in its longevity and adaptability across multiple processor generations. It was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and its variants continued through the Pentium M and Enhanced Pentium M (Yonah) lines. The architecture proved particularly notable for mobile computing: upon release of the Pentium 4-M and Mobile Pentium 4, NetBurst processors were found to be inefficient per clock and per watt compared to their P6 predecessors, running much hotter without significant performance advantages. Intel responded by modernizing the P6 design into the Pentium M, which became the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle.

The Core microarchitecture, launched on July 27, 2006 in the form of the Core 2 processor, is a derivative of P6. It introduced a 14-stage instruction pipeline, SSE4.1 support for 45 nm models, 64-bit x86-64 architecture support, increased FSB speeds up to 1600 MT/s, and larger L2 cache sizes up to 12 MB. The Core microarchitecture was Intel's final mainstream processor line to use FSB, with all later Intel processors based on Nehalem and later microarchitectures featuring an integrated memory controller and a QPI or DMI bus. While all these chips are technically derivatives of the Pentium Pro, the architecture has gone through several radical changes since its inception.

Did You Know?

• The Pentium Pro was the first x86 microprocessor designed by Intel to use dynamic translation of IA-32 instructions into RISC-like micro-operations, though the NexGen Nx586 did so earlier in 1994.
• The first Pentium M family processors (Banias) internally support PAE but do not show the PAE support flag in their CPUID information, causing some operating systems to refuse to boot on such processors.