Cooper Lake (microprocessor)
Third-generation Xeon Scalable for 4S and 8S servers.
Cooper Lake is the code name Intel gave to its third-generation Xeon Scalable processors, which replaced Cascade Lake-SP. These chips are designed for the 4-socket and 8-socket server market, while the 1-socket and 2-socket segments are handled by Ice Lake-SP. The lineup launched on June 18, 2020, with a maximum of 28 cores. Its microarchitecture is largely the same as Skylake, aside from a few minor tweaks. Compared to Cascade Lake, Cooper Lake offers faster DDR4-3200 memory (up from DDR4-2933), support for second-generation Optane memory, and double the number of UPI links. It also marks the first x86 CPU to include the bfloat16 instruction set, part of Intel's Deep Learning Boost (DPL) technology. Other improvements include support for up to 12 DIMMs of DDR4 memory per socket, with Xeon Platinum models handling up to eight sockets, Xeon Gold up to four, and Xeon Silver and Bronze up to two. The -H variant supports up to 1.12 TB of DDR4 per socket, while the -HL tier supports large DDR memory up to 4.5 TB.
Quick Facts
- Produced-Start
- June 18, 2020
- Soldby
- Intel
- Code
- 80706
- Clock
- 4.3
- Qpi-Slow-Unit
- 10.4
- Application
- 4S and 8S servers
- Microarch
- Skylake
- Arch
- x86-64
- Instructions
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, bfloat16
- Extensions
- AES-NI, CLMUL, RDRAND, TXT, FSGSBASE, MOVBE, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, MPX, TSX, VT-x, VT-d
Facts from the source article.
Lore & Background
Cooper Lake's microarchitecture is mostly identical to Skylake, aside from a few microarchitectural changes. It features faster memory support (DDR4-3200 over DDR4-2933), support for second-generation Optane memory, and double the UPI links over Cascade Lake. Cooper Lake is the first x86 CPU to support the new bfloat16 instruction set as part of Intel's Deep Learning Boost (DPL).
Reader's Guide
Cooper Lake represents Intel's focus on high-socket-count server configurations, specifically the 4S and 8S market segments, while Ice Lake-SP handled the 1S and 2S segment. Its introduction of bfloat16 instructions marked the first x86 implementation of that data format, aimed at deep learning workloads. The processor also expanded memory capacity with support for up to 12 DIMMs of DDR4 per socket, and offered two memory tiers: the -H tier supporting up to 1.12TB DDR4 per socket, and the -HL tier supporting up to 4.5TB of large DDR memory. The Xeon Platinum line supported up to eight sockets, Xeon Gold up to four, and Xeon Silver and Bronze up to two sockets. These features positioned Cooper Lake as a bridge between the Skylake-derived architecture and newer platforms, while delivering incremental improvements in memory bandwidth and interconnect speed.
Did You Know?
- It supports up to 12 DIMMs of DDR4 memory per CPU socket.
- The -HL memory tier supports up to 4.5TB of DDR4 per socket.
- Cooper Lake has double the UPI links compared to Cascade Lake.
More in Intel and AMD Microprocessors, Part 2 1-24
Spotted an error? Know more?
Reader corrections go straight into our review queue. Suggest an edit · How this site is sourced