TLS acceleration
Offloads processor-intensive TLS handshake to hardware accelerators.
TLS acceleration, originally called SSL acceleration, shifts the heavy computational load of public-key encryption for Transport Layer Security (TLS) and its predecessor, Secure Sockets Layer (SSL), onto dedicated hardware. This is usually done with a card inserted into a computer's PCI slot, which contains one or more coprocessors designed to handle most of the SSL processing. While some accelerators use standard off-the-shelf CPUs, most rely on custom ASIC and RISC chips to perform the bulk of the demanding calculations.
The most resource-intensive part of a TLS session is the handshake. During this phase, the TLS server (often a web server) and the TLS client (typically a web browser) negotiate parameters to secure the connection. They establish session keys—symmetric keys used for the duration of that session—but the encryption and signing of the handshake messages themselves rely on asymmetric keys, which demand far more processing power than the symmetric cryptography used to encrypt and decrypt the actual session data. A typical hardware TLS accelerator offloads only the handshake processing, leaving the server software to handle the less intensive symmetric cryptography for the data exchange. However, some accelerators manage all TLS operations and terminate the TLS connection entirely, so the server only sees decrypted connections. In some data centers, dedicated servers are used for TLS acceleration in a reverse proxy setup.
Modern x86 CPUs include hardware support for AES encryption and decryption, using the AES instruction set introduced by Intel in March 2008. Allwinner Technology incorporates a hardware cryptographic accelerator in its A10, A20, A30, and A80 ARM system-on-chip series, and all ARM CPUs feature acceleration in the later ARMv8 architecture. This accelerator handles the RSA public-key algorithm, several widely used symmetric-key algorithms, cryptographic hash functions, and a cryptographically secure pseudo-random number generator.
- Former name
- SSL acceleration
- Typical form factor
- separate card that plugs into a PCI slot
- Most expensive operation
- TLS handshake
- Key cryptography type offloaded
- asymmetric keys (public-key encryption)
- Modern x86 feature
- AES instruction set proposed by Intel in March 2008
- Arm acceleration series
- Allwinner A10, A20, A30, A80; later ARMv8 architecture
Lore & Background
TLS acceleration offloads the computationally expensive TLS handshake, where asymmetric keys are used for encryption and signature, to a hardware accelerator. Typically, the accelerator handles the handshake while server software processes the less intense symmetric cryptography of the actual data exchange, though some accelerators handle all TLS operations and terminate the connection, leaving the server seeing only decrypted connections. Data centers sometimes employ dedicated servers for TLS acceleration in a reverse proxy configuration.
TLS accelerators may use off-the-shelf CPUs, but most use custom ASIC and RISC chips to perform the difficult computational work. Modern x86 CPUs support Advanced Encryption Standard (AES) encoding and decoding in hardware using the AES instruction set proposed by Intel in March 2008. Allwinner Technology provides a hardware cryptographic accelerator in its A10, A20, A30 and A80 ARM system-on-chip series, and all ARM CPUs have acceleration in the later ARMv8 architecture, supporting RSA, symmetric-key algorithms, cryptographic hash functions, and a cryptographically secure pseudo-random number generator.
Reader's Guide
TLS acceleration is notable for offloading the processor-intensive public-key encryption of the TLS handshake to dedicated hardware, thereby freeing the main server CPU for other tasks. The article describes that the handshake is the most computationally expensive part of a TLS session, as it uses asymmetric keys, while the subsequent data exchange uses less demanding symmetric cryptography. By handling the handshake on a separate card with coprocessors—often custom ASIC or RISC chips—the accelerator improves server performance. Some accelerators go further by terminating the entire TLS connection, presenting decrypted traffic to the server. The article also notes that modern x86 CPUs have built-in AES hardware acceleration via the AES instruction set, and ARM CPUs in the later ARMv8 architecture include cryptographic acceleration for RSA, symmetric algorithms, hash functions, and random number generation. This integration of hardware acceleration into mainstream CPUs reflects the growing importance of efficient cryptographic processing in computing.
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