Direct memory access

Lore & Background

Standard DMA, also called third-party DMA, uses a DMA controller that can generate memory addresses and initiate memory read or write cycles. The controller contains hardware registers—a memory address register, a count register, and control registers—that the CPU writes and reads. To perform a transfer, the host processor initializes the DMA controller with a count of words and a memory address, then commands the peripheral to initiate the transfer. The DMA controller provides addresses and read/write control lines to system memory, incrementing its internal address register until the full block is transferred.

In bus mastering (first-party DMA), the CPU and peripherals can each be granted control of the memory bus. A peripheral that becomes a bus master can directly write to system memory without CPU involvement, providing memory address and control signals. Some measures must prevent bus contention, and the peripheral may have its own address and count registers.

DMA operates in several modes. Burst mode transfers an entire block in one contiguous sequence, rendering the CPU inactive for relatively long periods. Cycle stealing mode transfers one unit of data per bus request, interleaving transfers with CPU activity so the CPU is not idled as long. Transparent mode transfers data only when the CPU is not using the system buses, making the transfer free in terms of time but complex to implement.

Reader's Guide

DMA significantly reduces CPU overhead for data transfers compared to systems without DMA. It is used by many hardware subsystems, including disk drive controllers, graphics cards, network cards, sound cards, and dedicated DMA controllers. DMA is also used for intra-chip data transfer in some multi-core processors and can offload expensive memory operations such as large copies or scatter-gather operations from the CPU to a DMA controller. An implementation example is I/O Acceleration Technology. DMA is of interest in network-on-chip and in-memory computing architectures.

DMA can lead to cache coherency problems. In a system with a CPU cache and external memory accessible by DMA, stale values can be read if the cache is not flushed before a device access or invalidated after a device write. This is addressed either by hardware bus snooping (cache-coherent systems) or by software that flushes or invalidates cache lines (non-coherent systems). Hybrids exist where the secondary L2 cache is coherent while the L1 cache is managed by software.

In the original IBM PC, a single Intel 8237 DMA controller provided four channels for 8-bit transfers, limited to the first megabyte of RAM and 64 kB segments. The IBM PC/AT added a second 8237 controller, providing three additional channels (5–7) capable of 16-bit transfers and addressing up to 16 MB of memory. The lower four channels remained limited to 8-bit transfers.

Did You Know?

• DMA can be used for memory-to-memory transfers, offloading expensive operations like large copies from the CPU.
• In burst mode, the DMA controller transfers an entire block of data before releasing control of the system bus back to the CPU.
• The original IBM PC used a single Intel 8237 DMA controller with four channels limited to 8-bit transfers and 64 kB segments.

The Physical Foundation and Its Name

Computer hardware encompasses every tangible component that makes up a computing system. At its core sit the central processing unit, random-access memory, the motherboard, data storage drives, graphics and sound cards, and the enclosing case. Beyond the chassis, the category extends to peripherals like monitors, mice, keyboards, and speakers. The term itself is a deliberate contrast: hardware is called 'hard' because altering it is rigid and difficult, while software—essentially a collection of written instructions that hardware stores and executes—is 'soft' because it can be modified with relative ease. In practice, the two are interdependent. Software directs hardware to carry out every command and instruction, and together they constitute a functional computing platform. That said, purely hardware-only systems do exist, underscoring that software, while typical, is not an absolute prerequisite. The relationship between the rigid physical layer and the malleable instruction layer remains the foundational duality on which all modern computing rests.

From Gears to Universal Machines

The story of computing hardware stretches back to the seventeenth century. In 1642, Blaise Pascal crafted the Pascaline, a gear-driven mechanism capable of addition and subtraction. Three decades later, Gottfried Leibniz introduced his stepped reckoner, extending the repertoire to multiplication and division. Though plagued by fabrication limits and design flaws that rendered it unreliable, the Leibniz wheel it spawned continued to see practical use well into the 1970s. The nineteenth century brought Charles Babbage's difference engine, a mechanical calculator built for polynomial computations in astronomy, and his ambitious but never-constructed general-purpose machine. Babbage's blueprints anticipated punch-card input and output, a memory unit, an arithmetic component analogous to today's CPU, and even a rudimentary assembly-like language. In 1936, Alan Turing formalized the universal Turing machine, a stored-program model proving that no single machine could solve the decision problem. Meanwhile, George Boole's mid-nineteenth-century Boolean algebra—where every proposition is strictly true or false—laid the logical groundwork for the transistor circuits and integrated chips that define modern hardware. Turing also completed the design for the Automatic Computing Engine in 1945, another machine that never saw construction.

The Von Neumann Blueprint and Its Bottleneck

By the mid-1940s, advances in relay technology and vacuum tubes made the construction of working computers feasible. George Stibitz at Bell Laboratories and Howard Aiken at Harvard, whose MARK I drew on Babbage's earlier ideas, built relay-based machines. In 1945, John von Neumann, working on the ENIAC project at the University of Pennsylvania, articulated the architectural template that would govern most computers for decades. His design placed both data and programs in a single centralized memory, gave the CPU priority access to that memory, and included dedicated input and output units. Crucially, von Neumann used a single bus to shuttle data between components. That elegant solution to the storage problem—keeping programs and data side by side—introduced what is now called the Von Neumann bottleneck: when the system attempts to fetch both a program instruction and its associated data simultaneously, the shared bus becomes a choke point that throttles overall performance. Despite this limitation, the architecture's core principles of unified memory, a prioritized processing unit, and separate I/O channels remain the structural backbone of virtually every general-purpose computer in use today.

Instruction Sets, Parallelism, and the Performance Curve

The interface between hardware and software is defined by the instruction set architecture, and two dominant philosophies have shaped its evolution. CISC designs employ a broad expression set to reduce the total number of instructions a machine must issue. RISC, by contrast, trims the instruction set for simplicity and adds more registers, leveraging pipelining and caching to boost throughput. After RISC emerged in the 1980s, its architectures displaced CISC in power- and space-constrained applications such as mobile phones. Between 1986 and 2003, annual hardware performance gains exceeded fifty percent, and DRAM, flash, and magnetic disk storage all became exponentially denser and cheaper. That rapid pace has since slackened. In the twenty-first century, performance growth is increasingly driven by parallelism. Applications can be parallelized either by running the same function across multiple data regions (data parallelism) or by executing different tasks concurrently with limited interaction (task parallelism). Hardware strategies to exploit these include instruction-level pipelining, vector architectures, GPUs for data-parallel workloads, thread-level parallelism, and request-level parallelism. Cost pressure and shrinking profit margins continue to push manufacturers toward more efficient fabrication, reducing component rejection at quality assurance.