Coarse-grained reconfigurable array
A word-level reconfigurable fabric for energy-efficient dataflow acceleration.
A coarse-grained reconfigurable array (CGRA) is a type of spatial computing chip made up of many processing elements (PEs) linked by a programmable on-chip network that can be set up either before or during operation. By changing what each PE does and how data moves between them, the array can be tailored to match the dataflow of a specific computation—typically the inner part of a performance-heavy loop. In terms of trade-offs, a CGRA lands between the flexibility of a software-programmable processor and the energy efficiency of a fixed-function chip.
The basic units of a CGRA work on whole words of data and are reconfigured at a coarse level, which sets them apart from FPGAs. FPGAs can be rewired down to individual bits and logic gates, giving them enormous flexibility but also costing more in chip area, power, and setup time. General-purpose CPUs and GPUs are also very flexible, but they burn energy fetching and decoding instructions for every operation. An ASIC is the most power-efficient option because it is built for just one task, but it cannot be changed after manufacture. Because a CGRA operates at word granularity, it keeps much of the spatial, energy-saving parallelism of custom hardware while remaining reprogrammable through software.
The concept of a reconfigurable machine dates back to 1960, and the modern form of CGRAs took shape in the mid-1990s. Since then, they have been used in signal processing, wireless communication, and machine learning, appearing in both academic research chips and commercial products. Running a program on a CGRA requires a specialized compiler that maps the program’s dataflow graph onto the array, and this compilation step remains a major barrier to broader adoption.
Interest in CGRAs has grown because of a widening gap in the hardware landscape. As Dennard scaling ended and Moore’s law slowed, general-purpose processors stopped delivering automatic performance gains, pushing computer architecture toward specialization to improve performance per watt—especially for demanding workloads like neural networks. At one extreme, fixed-function ASICs achieve the highest efficiency but come with high non-recurring engineering costs and cannot be updated after fabrication. At the other extreme, von Neumann processors are fully programmable but inefficient in energy, with FPGAs sitting in a flexible but costly middle ground.
- First conceived
- 1960
- Modern form emerged
- mid-1990s
- Building block granularity
- word level
- Reconfiguration time
- nanoseconds
- Typical array organization
- two-dimensional array of processing elements
- Common interconnect topologies
- mesh, torus, crossbar switch
Lore & Background
The idea of a machine whose structure can be reconfigured for a computation dates to the 'fixed-plus-variable structure computer' proposed by Gerald Estrin in 1960. Coarse-grained arrays in the modern sense emerged in the mid-1990s, when several groups replaced the bit-level cells of an FPGA with word-level processing elements. Notable early designs include the KressArray, which introduced a two-dimensional mesh of reconfigurable datapath units; MATRIX, which combined a word-level datapath with a configurable interconnect; RaPiD and PipeRench, which organized their cells as reconfigurable pipelines; and MorphoSys, which paired a reconfigurable-cell mesh with a control processor for data-parallel media workloads.
Through the 2000s, designs grew larger and more tightly integrated. ADRES coupled a VLIW processor with a reconfigurable matrix; TRIPS explored a polymorphous array capable of exploiting instruction-, thread-, and data-level parallelism; and PACT XPP offered a self-reconfiguring commercial fabric. From the 2010s onward, research emphasized data movement and system integration: HyCUBE introduced a single-cycle multi-hop interconnect, Plasticine organized computation around pattern compute and pattern memory units, and the stream-dataflow (Softbrain) model decoupled memory streaming from the spatial datapath. The same period saw an open-source ecosystem take shape, including ultra-low-power edge arrays such as OpenEdgeCGRA, which is integrated with the X-HEEP RISC-V microcontroller in the HEEPsilon platform.
A handful of CGRAs have reached commercial silicon. Samsung’s Reconfigurable Processor (SRP), derived from ADRES, has appeared in systems-on-chip and in ultra-low-power biomedical variants; SambaNova commercialized its reconfigurable dataflow unit (RDU), a large dataflow accelerator built from pattern compute and pattern memory units and aimed at machine-learning training and inference.
Reader's Guide
CGRAs occupy a distinct niche in the hardware landscape, motivated by the widening gap between general-purpose processors and fixed-function ASICs as the end of Dennard scaling and the slowing of Moore’s law reduced automatic performance gains. At one extreme, fixed-function ASICs achieve the highest efficiency but incur high non-recurring engineering costs and cannot be changed after fabrication. At the other end, von Neumann processors are fully programmable but energy-inefficient, with FPGAs sitting in a flexible but costly middle ground. By operating at word granularity, a CGRA retains much of the spatial, energy-efficient parallelism of custom hardware while remaining reprogrammable in software.
The architecture is typically organized as a two-dimensional array of processing elements, each built around an arithmetic logic unit or functional unit, a small local register file, and configuration registers. PEs are connected by a programmable interconnect, commonly a mesh, torus, or crossbar. Most CGRAs are not standalone; the array is coupled to a host or control processor, often a VLIW, ARM, or RISC-V core. Programming a CGRA means loading a configuration into the array’s configuration memory, specifying each PE’s operation and routing. Because configuration is coarse-grained, a dedicated CGRA can switch to a new configuration in nanoseconds, orders of magnitude faster than an FPGA. Running a program on a CGRA depends on a specialized compiler that maps the program’s dataflow graph onto the array, a step that remains one of the main obstacles to wider adoption.
Did You Know?
- CGRAs were first envisioned in 1960 by Gerald Estrin as a 'fixed-plus-variable structure computer'.
- CGRAs have been applied to signal processing, wireless communication, and machine learning.
- SambaNova commercialized a reconfigurable dataflow unit (RDU) based on CGRA principles for machine-learning training and inference.
Frequently Asked Questions
What is a Coarse-grained reconfigurable array?
A CGRA is a spatial computing chip built from numerous small processing elements wired together through a programmable on-chip network. Each element can be reprogrammed to perform a different operation, and the interconnect can be rewired so the whole fabric mirrors the dataflow of a specific workload. In practice it accelerates the inner, compute-heavy portion of a loop by adapting its hardware structure on the fly.
Where does a CGRA sit between a CPU and an FPGA?
A CGRA occupies the middle ground: more adaptable than a fixed-function ASIC yet far more energy-efficient than a general-purpose software processor. Unlike an FPGA, its processing elements operate at word-level granularity rather than bit-level, and the fabric can be reconfigured in nanoseconds instead of the milliseconds an FPGA typically needs.
When were CGRAs first conceived and when did the modern form emerge?
The foundational idea dates to 1960, but the architecture we recognize today—two-dimensional grids of word-level PEs with programmable interconnects—crystallized in the mid-1990s. That is when researchers began treating the reconfigurable fabric as a practical, deployable accelerator for dataflow workloads rather than a purely academic concept.
What are the typical building blocks and interconnect topologies in a CGRA?
The standard layout is a two-dimensional array of processing elements, each working at word-level granularity. The on-chip network linking them most commonly uses a mesh, a torus, or a crossbar-switch topology, and the entire fabric can be reconfigured either statically before a task begins or dynamically while it is still running.
Why do hardware enthusiasts consider CGRAs important for the future of PC accelerators?
They offer a practical route to near-ASIC energy efficiency without giving up the adaptability of a programmable processor. Because the array's structure can be tailored to the exact dataflow of a performance-critical loop and then reprogrammed for a different algorithm in nanoseconds, a single CGRA die can serve many workloads that would otherwise each demand a dedicated chip.
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