Field-programmable gate array

Lore & Background

The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). Altera was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window that allowed users to shine an ultraviolet lamp on the die to erase the EPROM cells holding the configuration. Xilinx (now owned by AMD) produced the first commercially viable field-programmable gate array in 1985 – the XC2064 – which had 64 configurable logic blocks (CLBs) with two three-input lookup tables (LUTs). In 1987, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer implementing 600,000 reprogrammable gates; a patent related to the system was issued in 1992.

Altera and Xilinx continued unchallenged from 1985 to the mid-1990s when competitors sprouted up. By 1993, Actel (later Microsemi, now Microchip) served about 18 percent of the market. The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and volume of production. In the early 1990s, FPGAs were primarily used in telecommunications and networking; by the end of the decade, they found their way into consumer, automotive, and industrial applications. By 2013, Altera (31 percent), Xilinx (36 percent), and Actel (10 percent) together represented approximately 77 percent of the FPGA market.

Companies like Microsoft have started using FPGAs to accelerate high-performance, computationally intensive systems (such as the data centers operating their Bing search engine) due to the performance per watt advantage. Microsoft began using FPGAs to accelerate Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for their Azure cloud computing platform. Since 2019, modern generations of FPGAs have been integrated with other architectures like AI engines to target workloads in the artificial intelligence domain.

Reader's Guide

FPGAs are significant because they allow flexible reconfigurable computing, similar to computer software, enabling designs to be updated after shipping. They offer low non-recurring engineering costs relative to ASICs, though generally higher unit cost, making them advantageous for many applications. FPGAs are commonly used during the development of ASICs to speed up simulation processes. They also play a role in embedded system development by allowing system software development to start simultaneously with hardware, enabling system performance simulations at a very early phase, and allowing various system trials and design iterations before finalizing the system architecture. Contemporary FPGAs have ample logic gates and RAM blocks to implement complex digital computations, and can implement any logical function that an ASIC can perform. Some FPGAs have analog features such as programmable slew rate, quartz-crystal oscillator driver circuitry, on-chip RC oscillators, phase-locked loops, differential comparators, and a few mixed-signal FPGAs have integrated ADCs and DACs, allowing them to operate as a system on a chip (SoC). Modern FPGA families also include higher-level functionality fixed in silicon, such as multipliers, generic DSP blocks, embedded processors, high-speed I/O logic, and embedded memories, reducing area and increasing performance compared to building them from logical primitives.

Did You Know?

• The first commercially viable FPGA was the Xilinx XC2064 in 1985, which had 64 configurable logic blocks with two three-input lookup tables.
• By 2013, Altera, Xilinx, and Actel together represented approximately 77 percent of the FPGA market.
• Microsoft began using FPGAs to accelerate its Bing search engine in 2014 and deployed them across Azure data center workloads in 2018.

Roots in Xilinx's Parallel Vision

The AI engine architecture traces its lineage to Xilinx, a company long synonymous with field-programmable gate arrays. Xilinx's original ambition was not specifically about artificial intelligence despite the name; rather, it centered on accelerating signal processing and any workload where data parallelism could yield substantial gains. The first products to house these engines were the Versal adaptive compute acceleration platforms, which wove together scalar, adaptable, and intelligent processing cores linked by a Network on Chip. The inaugural systems, the VCK190 and VCK5000, packed 400 AI engines into a single layer, all communicating through a VC1902 NoC. Each engine carried 32 KB of local data memory and 16 KB of program storage, and could borrow memory from neighboring tiles to reach 128 KB at the cost of reducing the effective number of compute cores. The overarching design philosophy was one of dense, interconnected parallelism—each tile executing an independent function while cascading, streaming, and sharing memory with its peers through three distinct communication interfaces.

The AMD Acquisition and the Push Toward Accessibility

In 2022, the landscape shifted dramatically when AMD, a major American player in computing architecture, completed its acquisition of Xilinx. This transition placed the AI engine project under new corporate stewardship and opened the door to a far broader application space. AMD recognized that while the Versal architecture was technically capable, it presented a steep learning curve for the vast academic and industrial community. To address this, AMD partnered with third-party developers to release improved toolsets and software stacks designed to reduce the programming complexity that had kept many users at bay. The goal was straightforward: make the platform more productive and more programmable. C++ remained the primary language for declaring connections between engines and writing kernel logic, though alternative toolchains began offering support for other languages and higher levels of automation. This era marked a deliberate pivot from a niche FPGA-adjacent technology toward a more accessible, mainstream computing substrate.

Inside the Tile: A 7-Way VLIW Design

At the heart of each AI engine sits a 7-way VLIW processor that blends vector and scalar execution to perform multiple operations within a single clock cycle. The vector unit spans 128 bits and delivers SIMD capability, while a separate scalar unit handles control flow and sequential logic. Dedicated load and store units manage memory access, and the maximum vector register stretches to 1024 bits, meaning the effective vector width shifts depending on the data type in use. The architecture is statically scheduled, a design choice that trades dynamic flexibility for predictable timing but often produces code explosion, forcing developers to manually optimize kernels to keep instruction bloat in check. In the first generation, each tile carried 32 KB of data memory and 16 KB of program memory. Communication between tiles relied on three distinct interfaces—cascade, memory, and stream—each representing a different mechanism for one engine to talk to its neighbors. This tight, deterministic interconnect was what allowed hundreds of engines to operate as a coherent parallel fabric.

From AI Engines to XDNA: The NPU Era

By 2023, AMD introduced the second-generation AIE-ML architecture, adding support for AI-specific data types such as bfloat16 and enlarging memory to accommodate more intermediate computations while retaining the same vector processing core. From this generation onward, AMD began embedding AI engines alongside CPUs and GPUs inside modern Ryzen AI processors, where the engines are commonly called Compute Tiles. These self-contained blocks pair with Memory Tiles and Shim Tiles to form a unified fabric branded XDNA. XDNA 1 debuted on Ryzen AI Phoenix PCs, accompanied by the open-source Riallto tool to sustain AMD's programmability push. By late 2023 into early 2024, XDNA 2 arrived with the Strix series, offering more processing units to handle the heavier workloads of modern ML systems, alongside the open-source Ryzen AI SW toolchain for optimizing and deploying inference. As deep learning proliferates across industries, researchers increasingly classify XDNA architectures as Neural Processing Units, a category that also encompasses competing designs from companies such as Huawei and Tesla.