C to HDL
C to HDL tools convert C code into hardware description languages.
C to HDL tools take source code written in C or a C-like language and translate it into a hardware description language (HDL) like VHDL or Verilog. Once converted, the resulting code can be synthesized and implemented on a hardware device such as a field-programmable gate array (FPGA). Hardware implementations of the same design offer advantages over software: they consume less power (providing better performance per watt), run faster with lower latency, and support more parallelism and higher throughput. Despite these benefits, designing and verifying systems directly in HDL can be slow and labor-intensive. As a result, systems engineers typically write performance-critical modules in HDL while using a high-level language for other parts, then synthesize those high-level modules into HDL using C to HDL or high-level synthesis tools. This approach is also known as C to RTL, where RTL stands for register transfer level, the representation needed to implement a program in logic.
**History** Early work on C to HDL began in the 1990s at Oxford University, where Ian Page, Charles Sweeney, and colleagues created the Handel-C language. They founded Embedded Solutions Limited (ESL) in 1999 to commercialize their research, renaming it Celoxica in September 2000. In 2008, Celoxica sold its embedded systems division to Catalytic for $3 million; that division later merged to form Agility Computing. Mentor Graphics acquired Agility's C synthesis assets in January 2009. Celoxica continues to operate, focusing on hardware acceleration for financial transactions and other industries.
**Applications** C to HDL techniques are most often used for applications that run too slowly on general-purpose supercomputers. Common examples include bioinformatics, computational fluid dynamics (CFD), financial processing, and analysis of oil and gas survey data. Embedded systems that demand high performance or real-time data processing also benefit from this approach, as do system-on-chip (SoC) designs. C-to-VHDL compilers prove especially useful for large designs or code that may need future updates. Building a large application entirely in HDL can be extremely difficult and time-consuming; using a high-level language for such projects often reduces overall development time.
- Early developers
- Ian Page, Charles Sweeney and colleagues at Oxford University
- Early tool
- Handel-C
- Commercialization company
- Embedded Solutions Limited (ESL), renamed Celoxica in September 2000
- Sale year
- 2008
- Sale amount
- $3 million
- Acquiring company
- Catalytic, later merged to become Agility Computing
- Subsequent acquisition
- Mentor Graphics acquired Agility's C synthesis assets in January 2009
Lore & Background
Early development on C to HDL was done by Ian Page, Charles Sweeney and colleagues at Oxford University in the 1990s who developed the Handel-C language. They commercialized their research by forming Embedded Solutions Limited (ESL) in 1999 which was renamed Celoxica in September 2000. In 2008, the embedded systems departments of Celoxica was sold to Catalytic for $3 million and which later merged to become Agility Computing. In January 2009, Mentor Graphics acquired Agility's C synthesis assets. Celoxica continues to trade concentrating on hardware acceleration to process transactions in the financial sector and other industries.
C to HDL techniques are most commonly applied to applications that have unacceptably high execution times on existing general-purpose supercomputer architectures. Examples include bioinformatics, computational fluid dynamics (CFD), financial processing, and oil and gas survey data analysis. Embedded applications requiring high performance or real-time data processing are also an area of use. System-on-chip (SoC) design may also take advantage of C to HDL techniques. C-to-VHDL compilers are very useful for large designs or for implementing code that might change in the future. Designing a large application entirely in HDL may be very difficult and time-consuming; the abstraction of a high level language for such a large application will often reduce total development time. Furthermore, an application coded in HDL will almost certainly be more difficult to modify than one coded in a higher level language. If the designer needs to add new functionality to the application, adding a few lines of C code will almost always be easier than remodeling the equivalent HDL code. Flow to HDL tools have a similar aim, but with flow rather than C-based design.
Reader's Guide
C to HDL tools are significant because they bridge the gap between software and hardware design, allowing systems engineers to use high-level languages for parts of a design while reserving HDL for critical modules. This approach reduces development time and simplifies modifications, as adding functionality in C is easier than remodeling HDL. The methodology is applied to computationally intensive fields such as bioinformatics, CFD, financial processing, and oil and gas survey data analysis, as well as embedded and SoC designs. The history of C to HDL includes early work at Oxford University leading to the Handel-C language and commercialization through Celoxica, which later sold its embedded systems division. The acquisition of Agility's C synthesis assets by Mentor Graphics in 2009 indicates ongoing industry interest. The article lists numerous example tools, including SmartHLS, CBG CtoV, Catapult C, and open-source initiatives like FpgaC, showing a diverse ecosystem. C to HDL remains relevant for hardware acceleration in sectors like finance, where Celoxica continues to operate.
Did You Know?
- C to HDL is also called C to RTL, where RTL stands for register transfer level.
- Celoxica was originally named Embedded Solutions Limited (ESL) and was renamed in September 2000.
Origins and the IBM PC Legacy
The concept of a Basic Input/Output System traces back to 1975, when Gary Kildall coined the term for the machine-specific layer of the CP/M operating system that loaded at boot time and spoke directly to hardware. That early design established a pattern: a small, hardware-aware program sitting between the operating system and the physical components of a machine. When IBM built its personal computer, the BIOS firmware was proprietary to the company, and its interface effectively became the de facto standard for the entire PC ecosystem. Competitors who wanted to build compatible machines—Compaq, Phoenix Technologies, AMI, and others—had to reverse engineer IBM's firmware to create their own versions. The architecture also evolved with IBM's PS/2 line, where the System BIOS was split into two distinct halves: a Compatibility BIOS (CBIOS) preserving backward compatibility with DOS-era software, and an Advanced BIOS (ABIOS) offering new interfaces tailored to multitasking operating systems like OS/2. This dual-mode approach reflected the transitional moment when the industry was moving beyond the single-tasking world of the 1980s.
The Boot Sequence and Hardware Interface
When a legacy PC powers on, the BIOS firmware begins a carefully sequenced routine. It performs a power-on self-test, or POST, initializing and verifying the system's hardware components. Once that check passes, the firmware loads a boot loader from a mass storage device, which then initializes the operating system kernel. During the DOS era, the BIOS played an even more central role: it exposed interrupt calls covering the keyboard, display, storage, and other input/output devices. These interrupts gave application programmers a standardized interface, so software could interact with hardware without knowing the specifics of the underlying chipset. Modern operating systems, however, largely abandon these interrupt calls once startup is complete. Beyond the motherboard firmware, peripheral cards such as hard-disk host bus adapters and video cards carry their own option ROM code. This extension firmware runs before the operating system loads, testing and initializing its hardware, adding new BIOS services, or replacing existing ones. A SCSI controller, for instance, typically ships with an option ROM that extends BIOS support to drives connected through that controller, and in principle an option ROM could implement an entirely different boot path such as network booting.
From Jumpers to Flash Memory
The original IBM PC and XT offered no interactive way to configure the system. If the power-on self-test failed before a video adapter was initialized, the user would see error codes on screen or hear coded series of beeps. Hardware options were set physically, using switches and jumpers on the main board and expansion cards. The IBM AT stored configuration settings in battery-backed RAM, but changing those settings required a bootable program on a floppy disk supplied with the computer; lose the disk and the settings were locked in. The same limitation applied to machines with an EISA bus, whose configuration program was called the EISA Configuration Utility. The mid-1990s brought a turning point: BIOS ROMs began including a setup utility accessible at power-up through a particular key sequence, letting users navigate interactive menus to configure hardware. On the storage side, the shift from a fixed ROM chip to flash memory was equally significant. Flash memory could be rewritten without removing the chip, enabling end-users to push firmware updates that added features or patched bugs. That same rewritability, however, introduced new risks: a failed BIOS upgrade could brick the motherboard, and the writable firmware opened a door for BIOS rootkits.
The UEFI Successor and the End of an Era
The Unified Extensible Firmware Interface was designed as a direct successor to the legacy PC BIOS, aiming to address its accumulated technical limitations. UEFI firmware can include legacy BIOS compatibility layers to keep older operating systems and option cards functioning, but the industry has been steadily moving away from that fallback. Intel began phasing out its support for booting from the BIOS interface between 2020 and 2024, with the exact timeline varying by platform. On the software side, Microsoft's Windows 10 stands as the last version of Windows to officially support running on PCs that use legacy BIOS firmware. Windows 11, by contrast, requires a UEFI-compliant system, with the narrow exception of IoT Enterprise editions starting from version 24H2. The broader picture is one of a decades-old architecture being retired. The BIOS, in its various forms—from the CP/M-era concept through the IBM PC's proprietary firmware to the flash-memory implementations of the 1990s and 2000s—served as the foundational layer between hardware and software for an entire generation of personal computers. Its replacement by UEFI marks the close of that era, even as compatibility shims ensure that the old interface lingers in the background for a while longer.
Frequently Asked Questions
What is C to HDL?
C to HDL refers to a family of compiler tools that accept C or C-like source code and emit a hardware description language such as VHDL or Verilog. The generated HDL can then be synthesized and mapped onto an FPGA, giving the design hardware-level speed and parallelism.
Who created the first C to HDL tool?
Ian Page, Charles Sweeney, and their team at Oxford University built Handel-C, the earliest known C-to-HDL compiler. The technology was later spun out into a company called Embedded Solutions Limited, which rebranded as Celoxica in 2000.
Why would I use C to HDL instead of writing Verilog or VHDL directly?
Hand-coding and verifying designs in HDL is slow and error-prone, so C to HDL tools let you work in a familiar high-level language while still capturing the lower latency, greater parallelism, and better power efficiency that a hardware implementation provides.
What happened to Celoxica?
Celoxica was sold to Catalytic in 2008 for roughly three million dollars. Catalytic subsequently merged to form Agility Computing, which inherited the C-to-HDL product line.
What hardware platform does C to HDL target?
The primary target is a field-programmable gate array (FPGA), where the synthesized HDL runs as dedicated circuitry. This gives the design significantly higher throughput and lower energy consumption per operation compared to executing the same logic as software on a CPU.
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