Dataflow architecture

Lore & Background

An early precursor to streaming and dataflow concepts was IBM's Harvest (7950), built for the NSA in 1962, which processed continuous streams of data operands through dedicated logical and lookup pipelines. Hardware architectures for dataflow were a major research topic in the 1970s and early 1980s, with Jack Dennis of MIT pioneering static dataflow architectures, while the Manchester Dataflow Machine and MIT Tagged Token architecture were major projects in dynamic dataflow. Research never overcame problems such as efficiently broadcasting data tokens in massively parallel systems, efficiently dispatching instruction tokens, building content-addressable memory (CAM) large enough for real programs, and the fine-grained nature of instructions and data dependencies making distribution over large networks inefficient.

Static dataflow machines use conventional memory addresses as data dependency tags and do not allow multiple instances of the same routines to execute simultaneously. Dynamic dataflow machines use content-addressable memory (CAM) with tags to facilitate parallelism. Programs are loaded into the CAM; when all tagged operands of an instruction become available, the instruction is marked ready for execution (activating or firing). Output data is sent with its tag to the CAM, marking dependent instructions as ready. Instructions and data are transmitted as packets (instruction tokens and data tokens), enabling large-scale parallel execution. Data tokens are transient messages, not permanently stored in memory.

Out-of-order execution (OOE), dominant since the 1990s, is a form of restricted dataflow that uses an execution window following sequential order but allowing instructions to complete in data dependency order. The logical complexity of tracking dependencies restricts OOE CPUs to 2-6 execution units and execution window sizes of 32 to 200 instructions. In October 2024, NextSilicon announced the Maverick-2 accelerator, a dataflow chip for HPC workloads, and partnered with Sandia National Laboratories for the Spectra supercomputer. In July 2025, Efficient Computer reported building a dataflow chip called Electron E1.

Reader's Guide

Dataflow architecture stands apart as a radical approach to parallelism that has been least successful in general-purpose computing, as noted by Maurice Wilkes in 1995. Its primary significance lies in specialized hardware domains such as digital signal processing, network routing, graphics processing, telemetry, data warehousing, and artificial intelligence, where it has been successfully implemented. The architecture's deterministic nature enables programmers to manage complex tasks like processor load balancing, synchronization, and access to common resources. Synchronous dataflow architectures tune to match real-time data path applications such as wire speed packet forwarding. The concept remains highly relevant in software, including database engine designs and parallel computing frameworks. Out-of-order execution, the dominant computing paradigm since the 1990s, is a restricted form of dataflow that has brought some of its principles into mainstream CPUs, though limited by logical complexity to small execution windows and few execution units. Recent developments include the NextSilicon Maverick-2 accelerator for HPC (announced October 2024) and the Efficient Computer Electron E1 chip (reported July 2025), indicating ongoing interest in dataflow hardware. The clash of terminology with dataflow programming, a subarea of parallel programming, adds to the complexity of the field.

Did You Know?

• Dataflow architectures have no program counter; instruction execution is based solely on input argument availability.
• Out-of-order execution, dominant since the 1990s, is a restricted form of dataflow limited to 2-6 execution units and window sizes of 32 to 200 instructions.

Origins & Early Foundations

The conceptual roots of computer architecture stretch back to the written exchanges between Charles Babbage and Ada Lovelace, who outlined the design of the analytical engine. A pivotal leap came in 1936 when Konrad Zuse, while constructing the Z1 machine, filed two patent applications proposing that machine instructions could reside in the same storage as data—a principle we now call the stored-program concept. The 1940s brought two landmark documents: John von Neumann's 1945 "First Draft of a Report on the EDVAC," which laid out an organization of logical elements, and Alan Turing's more granular "Proposed Electronic Calculator for the Automatic Computing Engine," also from 1945, which explicitly cited von Neumann's work. Together these early papers established the foundational vocabulary and structural thinking that would shape every subsequent generation of computer design.

The Term "Architecture" & Its Institutionalization

The word "architecture" entered computer literature through the work of Lyle R. Johnson and Frederick P. Brooks, Jr., both members of the Machine Organization department at IBM's main research center in 1959. Johnson, tasked with writing a proprietary research communication about Stretch—an IBM-developed supercomputer built for Los Alamos National Laboratory—found that his descriptions of formats, instruction types, hardware parameters, and speed enhancements sat at a level he called "system architecture," a label he felt was more useful than "machine organization." Brooks, himself a Stretch designer, later opened Chapter 2 of his book Planning a Computer System: Project Stretch with the observation that computer architecture, like architecture in other fields, is the art of determining a user's needs and designing to meet them within economic and technological constraints. Brooks subsequently helped develop the IBM System/360 line, where "architecture" solidified as a noun meaning "what the user needs to know." That line was eventually succeeded by several compatible families, including the current IBM Z line, and users gradually began applying the term in many less formal ways.

Evolution of Design Methodology

The earliest computer architectures were sketched on paper and then directly translated into final hardware. A significant shift occurred when designers began building physical prototypes in transistor–transistor logic (TTL) form—examples include the prototypes of the 6800 and the PA-RISC—allowing teams to test and refine their designs before committing to a final silicon implementation. By the 1990s, the workflow had transformed again: new architectures were typically "built," tested, and iterated inside a simulator running on another computer architecture, or implemented as a soft microprocessor on a field-programmable gate array (FPGA), or both, before any final hardware was produced. This progression from paper to physical TTL boards to virtual simulation environments reflects a broader trend toward reducing the cost and risk of committing to a particular design, while also enabling far more rapid cycles of experimentation and refinement.

Subcategories & Specialized Layers

Computer architecture is organized around three core subcategories. Instruction set architecture (ISA) defines the machine code a processor executes, along with word size, memory address modes, registers, and data types. Microarchitecture—sometimes called "computer organization"—describes how a specific processor implements that ISA; for instance, CPU cache size is a microarchitecture concern with no bearing on the ISA itself. Systems design encompasses all other hardware in the computing system, including direct memory access, virtualization, and multiprocessing. Beyond these core areas, larger firms like Intel work with additional layers estimated in 2002 to account for roughly one percent of all architecture work: macroarchitecture (layers more abstract than microarchitecture), assembly instruction set architecture (where smart assemblers translate a common abstract language into slightly different machine code per implementation), and programmer-visible macroarchitecture (where standards like C, C++, or Java define a consistent interface that abstracts away underlying ISA and microarchitecture differences). Microcode and pin architecture further extend the design space, letting chip designers present stable instruction interfaces across hardware revisions or expose flexible hardware functions to external platforms.