SHA instruction set
Hardware acceleration for SHA hashing across major CPU architectures.
The SHA instruction set refers to processor extensions found in ARM, Power, RISC-V, and x86 architectures that accelerate the Secure Hash Algorithm (SHA) family in hardware. On ARM, SHA-1 and SHA-256 instructions were introduced as optional features in Arm V8.0 (2011), with specific instructions like SHA1C and SHA256H. SHA-512 and SHA-3 instructions followed as optional features in Arm V8.2, including SHA512H and EOR3. A scalable vector extension (SVE) version of the SHA-3 instructions became optional in Arm V9.0. For Power ISA v2.07 (May 2013), vector instructions for SHA-256 and SHA-512 sigma functions—vshasigmaw and vshasigmad—were added, each performing one of four sigma operations from the SHA-2 standard based on parameters. RISC-V includes SHA-2 instructions as part of the Zknh extension, ratified in November 2021. These differ between RV32 and RV64 for SHA-512, with RV32 splitting sigma operations into high and low halves (e.g., sha512sig0h and sha512sig0l), while RV64 uses single instructions like sha512sig0. On x86, Intel specified four SSE-based SHA-1 instructions and three for SHA-256 in 2013. SHA-512 instructions, using AVX with a V prefix (VSHA512RNDS2, VSHA512MSG1, VSHA512MSG2), arrived in Arrow Lake and Lunar Lake in 2024. AMD supports the original SHA set from Zen (2017) onward. Intel supports it from Goldmont (2016) for Atoms, Cannon Lake and Ice Lake for mobile, and Rocket Lake for desktops; the newer SHA-512 set is limited to Arrow Lake and Lunar Lake.
- Arm sha1 sha256 introduced
- Arm V8.0 architecture (2011)
- Arm sha512 sha3 introduced
- Arm V8.2 architecture
- Power sha2 sigma instructions added
- Power ISA v.2.07 (May 2013)
- Risc v zknh extension ratified
- November 2021
- X86 original sha extensions specified
- 2013 by Intel
- X86 sha512 introduced
- Arrow Lake and Lunar Lake (2024)
- Amd original sha support start
- Zen (2017)
Lore & Background
The SHA instruction set originated as optional features in the ARM architecture, with SHA-1 and SHA-256 instructions appearing in Arm V8.0 in 2011. Later, SHA-512 and SHA-3 instructions were added in Arm V8.2, and a scalable vector extension (SVE) version of SHA-3 appeared in Arm V9.0. Power ISA v.2.07, released in May 2013, added vector instructions for the Sigma functions of SHA-256 and SHA-512. RISC-V ratified the Zknh extension for SHA2 instructions in November 2021, with separate instruction sets for SHA-256 (common to RV32 and RV64) and SHA-512 (differing between RV32 and RV64 due to word size). On x86, Intel specified the original SSE-based SHA-1 and SHA-256 instructions in 2013, and later introduced SHA-512 instructions in Arrow Lake and Lunar Lake processors in 2024. AMD processors from Zen (2017) onward support the original SHA instruction set.
Reader's Guide
The SHA instruction set is significant because it provides hardware-level acceleration for cryptographic hashing, a core operation in security protocols, digital signatures, and blockchain technologies. By offloading SHA computations to dedicated instructions, processors can perform hashing much faster than software implementations. The article notes that these extensions span four major CPU architectures—ARM, Power, RISC-V, and x86—indicating broad industry adoption. On x86, Intel's original SHA extensions were supported starting with Goldmont Atom (2016) and Cannon Lake mobile (2018/2019), while AMD's Zen line (2017) also included them. The newer SHA-512 instructions on x86 arrived only in 2024 with Arrow Lake and Lunar Lake. ARM's implementation evolved across architecture versions, with SHA-1 and SHA-256 as optional features in V8.0, and SHA-512 and SHA-3 in V8.2. RISC-V's Zknh extension, ratified in 2021, provides SHA-256 and SHA-512 instructions, with RV32 requiring split operations for SHA-512. Power ISA's approach uses vector instructions for the Sigma functions. The legacy of these extensions is their role in making cryptographic hashing a standard, accelerated capability in modern processors.
Did You Know?
- ARM's SHA-1 and SHA-256 instructions appeared as optional features in the Arm V8.0 architecture introduced in 2011.
- RISC-V's SHA2 instructions are part of the Zknh extension, ratified in November 2021.
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