Network processor

Lore & Background

Network processors evolved from the need to handle packet data in modern telecommunications networks, which use packet switching for voice, video, and data, as opposed to older analog signal networks like the PSTN or analog TV/Radio. These processors have specific features or architectures to enhance and optimize packet processing. Over time, they evolved into more complex and flexible integrated circuits, becoming programmable so that a single hardware design can undertake multiple functions depending on the installed software.

In 2013, Reconfigurable Match-Tables (RMT) were introduced to allow switches to operate at high speeds while maintaining flexibility regarding which network protocols are enabled and how they are processed. The P4 programming language is used to program these chips. Barefoot Networks was based around RMT processors and was later purchased by Intel in 2019. An RMT pipeline consists of three main stages: a programmable parser, Match-Action tables, and a programmable deparser. The parser reads packet chunks to identify protocols and extracts fields into a Packet Header Vector (PHV). Match-Action tables match fields using a crossbar and CAM memory, producing instructions that operate on the PHV. The deparser reassembles the modified packet.

Network processors are used in equipment such as routers, software routers, switches, firewalls, session border controllers, intrusion detection and prevention devices, network monitoring systems, and network security devices (secure cryptoprocessors). Generic functions include pattern matching, key lookup, computation, data bitfield manipulation, queue management, control processing, and quick allocation and re-circulation of packet buffers.

Reader's Guide

Network processors are significant because they provide a programmable, optimized platform for handling the high-speed packet processing required in modern telecommunications networks. Their evolution from fixed-function circuits to programmable devices allowed a single hardware design to serve multiple roles, reducing the need for specialized chips. The introduction of Reconfigurable Match-Tables in 2013 further enhanced flexibility by enabling switches to support new protocols without hardware changes, using the P4 programming language. This approach was later extended to Network Interface Controllers via FlexNIC, allowing servers to send and receive packets at high speeds with reduced CPU overhead. Architecturally, network processors employ pipelines of processors, parallel processing with multithreading, specialized microcoded engines, and multicore designs for higher-layer processing. Traffic management, once handled by separate co-processors, became an integral part of the network processor, occupying substantial silicon area. Modern network processors also include low-latency on-chip interconnection networks for efficient inter-core communication. Their legacy lies in enabling a wide range of network equipment—from routers and switches to security devices—to perform tasks such as packet forwarding, quality of service enforcement, access control, encryption, and TCP offload processing, all through software-defined functionality.

Did You Know?

• Network processors are typically software programmable and have generic characteristics similar to general purpose central processing units.
• Reconfigurable Match-Tables were introduced in 2013 and are programmed using the P4 language.
• Barefoot Networks, based on RMT processors, was purchased by Intel in 2019.
• FlexNIC applies the RMT model to Network Interface Controllers to reduce CPU overhead.