Network on a chip
A router-based packet switching network on an integrated circuit.
A network on a chip (NoC, pronounced either en-oh-SEE or knock) is a communication subsystem built into an integrated circuit, primarily used to connect the various modules inside a system on a chip (SoC). These modules are typically semiconductor IP cores that represent different functions of a computer system and are designed to be modular in a network-science sense. The NoC itself is a router-based packet-switching network that links these SoC modules. By applying computer networking theory and methods to on-chip communication, NoC technology offers significant improvements over older bus and crossbar architectures.
The structure of NoCs can handle both synchronous and asynchronous clock domains, a technique known as clock domain crossing, or can use unclocked asynchronous logic. They support globally asynchronous, locally synchronous electronics, which lets each processor core or functional unit on the SoC run with its own clock domain. Architecturally, NoCs often model sparse small-world networks and scale-free networks to keep the number, length, area, and power consumption of wires and point-to-point connections low. The topology of the network determines the physical layout and connections between nodes and channels; messages travel through hops, and each hop’s channel length depends on this topology. Topology heavily influences both latency and power consumption, and because it dictates the number of alternative paths between nodes, it also affects traffic distribution, bandwidth, and overall performance.
Traditionally, integrated circuits used dedicated point-to-point connections with one wire per signal, leading to dense networks. For large designs, this approach has several physical drawbacks: power consumption grows quadratically with the number of interconnections, wires take up a lot of chip area, and in nanometer CMOS technology, interconnects dominate performance and dynamic power dissipation—signal propagation across the chip can require multiple clock cycles, adding parasitic capacitance, resistance, and inductance. The sparsity and locality of connections in a NoC improve on these issues. Because wires in NoC links are shared by many signals, a high level of parallelism is possible: all data links can operate simultaneously on different data packets.
- Proposed year
- 2002
- First research symposium
- Princeton University, May 2007
- Second ieee symposium
- Newcastle University, April 2008
- Acronym pronunciation
- en-oh-SEE or knock
Lore & Background
In the 2000s, researchers had started to propose a type of on-chip interconnection in the form of packet switching networks in order to address the scalability issues of bus-based design. Preceding researchers proposed a design that routes data packets instead of routing the wires. Then, the concept of 'networks on chip' was proposed in 2002. NoCs improve the scalability of systems-on-chip and the power efficiency of complex SoCs compared to other communication subsystem designs. They are an emerging technology, with projections for large growth in the near future as multicore computer architectures become more common.
NoCs can span synchronous and asynchronous clock domains, known as clock domain crossing, or use unclocked asynchronous logic. NoCs support globally asynchronous, locally synchronous electronics architectures, allowing each processor core or functional unit on a system on chip to have its own clock domain. NoC architectures typically model sparse small-world networks (SWNs) and scale-free networks (SFNs) to limit the number, length, area and power consumption of interconnection wires and point-to-point connections.
The topology determines the physical layout and connections between nodes and channels. The message traverses hops, and each hop's channel length depends on the topology. The topology significantly influences both latency and power consumption. Furthermore, since the topology determines the number of alternative paths between nodes, it affects the network traffic distribution, and hence the network bandwidth and performance achieved.
Reader's Guide
Traditionally, ICs have been designed with dedicated point-to-point connections, with one wire dedicated to each signal. This results in a dense network topology. For large designs, this has several limitations: it requires power quadratic in the number of interconnections, wires occupy much of the chip area, and in nanometer CMOS technology, interconnects dominate both performance and dynamic power dissipation. Sparsity and locality of interconnections in the communications subsystem yield several improvements over traditional bus-based and crossbar-based systems. The wires in the links of the network-on-chip are shared by many signals, achieving a high level of parallelism because all data links in the NoC can operate simultaneously on different data packets. As the complexity of integrated systems keeps growing, a NoC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures. Some researchers think that NoCs need to support quality of service (QoS) for real-time computation and for multiple concurrent users sharing resources in a public cloud computing infrastructure. Many challenging research problems remain at all levels, from the physical link level through the network level, and all the way up to the system architecture and application software. Research has been conducted on integrated optical waveguides and devices comprising an optical network on a chip (ONoC), and a possible way to increase performance is to use wireless communication channels between chiplets – named wireless network on chip (WiNoC).
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