High-level synthesis

Lore & Background

Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level synthesis. Scheduling partitions the algorithm into control steps that define states in a finite-state machine, while allocation and binding map instructions and variables to hardware components. First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler, using Verilog or VHDL as input languages, but it was not widely adopted and was end-of-lifed in early 2004. Forte Design Systems later introduced Cynthesizer using SystemC, which was adopted by many Japanese companies in 2000, leading to the first high-level synthesis tapeout by Sony in 2001. Adoption in the United States started in earnest in 2008.

In 2006, an efficient and scalable 'SDC modulo scheduling' technique was developed on control and data flow graphs, later extended to pipeline scheduling. This technique uses integer linear programming but shows the underlying constraint matrix is totally unimodular after approximating resource constraints, allowing optimal polynomial-time solution. The SDC scheduling algorithm was implemented in the xPilot HLS system at UCLA, licensed to AutoESL Design Technologies, which was acquired by Xilinx in 2011, becoming the base of Vivado HLS and Vitis HLS. The most common source inputs are ANSI C/C++, SystemC, and MATLAB, often including a bit-accurate executable specification for numerical refinement.

Reader's Guide

High-level synthesis is significant because it enables hardware designers to work at a higher level of abstraction, decoupling behavior from low-level circuit mechanics such as clock-level timing. The process transforms untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation. This allows a single algorithmic description to generate a variety of hardware microarchitectures, trading off execution speed for hardware complexity. Verification of the RTL is an important part of the process. The legacy of HLS includes its adoption in industry, with tools like Cynthesizer enabling the first tapeout in 2001, and the SDC scheduling technique being recognized by the FPGA and Reconfigurable Computing Hall of Fame in 2022. The acquisition of AutoESL by Xilinx led to widely used tools for FPGA designs. Interface synthesis, a key capability, allows designers to accept pure C/C++ descriptions and automatically control timing and communications protocols, enabling exploration of hardware interface options without embedding protocols in the source.

Did You Know?

• The first high-level synthesis tapeout was achieved in 2001 by Sony using Cynthesizer.
• The SDC modulo scheduling technique was inducted into the FPGA and Reconfigurable Computing Hall of Fame in 2022.
• Synopsys introduced the first generation behavioral synthesis tool, Behavioral Compiler, in 1994, but it was end-of-lifed in early 2004.
• AutoESL, which developed the base for Xilinx HLS tools, was a spin-off from UCLA.