Hollywood (graphics chip)

Lore & Background

The initial Hollywood-A revision was built on a 90 nm process and contained three dies. The first die, codenamed Vegas, handled most of the chip's functions. The second die, codenamed Napa, housed the high-speed RAM, while a third die contained EEPROM. The Hollywood-1 revision, codenamed Bollywood, was manufactured on a 65 nm process and merged Napa and Vegas into a single die.

The Texture Environment Unit (TEV) is a unique piece of hardware exclusive to the GameCube and Wii. The Wii inherited the TEV from Flipper, and the TEV is—to use an analogy from Factor 5 director Julian Eggebrecht—'like an elaborate switchboard that makes the wildest combinations of textures and materials possible.' The TEV pipeline combines up to 8 textures in up to 16 stages at once. Each stage can apply a multitude of functions to the texture. This was frequently used to simulate pixel shader effects such as bump-mapping, or to perform effects such as cel shading. On the GameCube, Factor 5's Star Wars: Rogue Squadron II used the TEV for the targeting computer effect and the simulated volumetric fog. The Wii's TEV unit and TEV capabilities are no different from the GameCube's, excluding indirect performance advantages from the faster clock speeds.

Hollywood contains an ARM926EJ-S core. The internal name for this core is IOP, but it is commonly known as Starlet. This embedded microprocessor runs the Wii's IOS operating system, and handles various I/O functions, including wireless communication, USB, SD card access, optical disc reading, and internal flash storage. Starlet also manages security functions, including cryptography, ensuring the console remains secure even if the main Broadway processor is compromised. Hollywood includes hardware implementations of AES and SHA-1 to speed up Starlet's security functionality. Starlet communicates with Broadway via an inter-process communication mechanism and can reboot Broadway or provide it with executable code at any time.

Reader's Guide

Hollywood's significance lies in its role as the integrated graphics and I/O solution for the Wii, a console that achieved broad market success. By updating the GameCube's Flipper GPU with a 1.5x clock speed increase to 243 MHz, Hollywood enabled more advanced visual effects while maintaining backward compatibility with the GameCube's fixed-function pipeline architecture. The inclusion of the Texture Environment Unit (TEV), inherited from Flipper, allowed developers to simulate pixel shader effects like bump-mapping and cel shading through a unique multi-texture blending pipeline, despite the lack of programmable shader hardware. The SoC's integration of the Starlet ARM coprocessor for I/O and security was a notable design choice, offloading system management and cryptographic tasks from the main Broadway CPU. The transition from a three-die 90 nm design (Hollywood-A) to a two-die 65 nm design (Hollywood-1) reflects a typical process shrink for cost and power reduction. The article notes that some performance figures—such as ~30 GB/s internal bandwidth and ~18 million polygons/second—are speculative, derived by scaling confirmed GameCube data by 1.5 based on clock speed differences. This conservative architectural approach, combined with the TEV's flexibility, defined the Wii's graphical capabilities throughout its lifecycle.

Did You Know?

• Hollywood was designed by ATI for Nintendo's Wii home video game console.
• The GPU in Hollywood is an updated version of the GameCube's Flipper, running at 243 MHz—1.5 times faster.
• The Hollywood-1 revision, codenamed Bollywood, merged the Vegas and Napa dies into a single die on a 65 nm process.

Branding and the Long Lineage

The story of AMD's graphics processors is one of continuous rebranding and reorganization. In the earliest days, chips shipped under names like Radeon SDR, DDR, LE, and VE before being retroactively slotted into a numbered scheme when the Radeon 8000 series arrived. The Wonder, Mach, and Rage series represent even earlier eras, with the Rage line offering only software-implemented OpenGL 1.0 for generic 2D work. The corporate identity itself shifted: ATI trademarks gave way to AMD trademarks beginning with the Radeon HD 6000 desktop line and the AMD FirePro professional line. Internal codenames tell their own story, progressing through geographic and geological themes—Evergreen, Northern Islands, Southern Islands, Sea Islands, Volcanic Islands, Arctic Islands—before the Vega and Navi generations (1X through 4X) took over. Each generation carried its own marketing name, codename, and positioning, making the full lineage a complex web of overlapping product families spanning from the mid-1990s into the present.

The Codec Acceleration Arms Race

Video decoding hardware tells a clear story of incremental capability gains across AMD/ATI's GPU generations. The R100 introduced the first Video Immersion engine, and the R200 doubled down with Video Immersion II. By the R300 era, a dedicated Video Shader was added alongside the second-generation immersion block. The R410 and R420 generations brought Video Shader HD, with the R420 also supporting DXVA for hardware-assisted decoding. The R520 marked a branding shift to Avivo Video, and the R600 paired Avivo HD with the first UVD 1.0 block. Subsequent generations steadily bumped UVD versions: R700 offered UVD 2 and 2.2, Evergreen reached 2.3, and Northern Islands introduced UVD 3 (though the HD 67xx retained UVD 2.2). Southern Islands added VCE 1.0 for encoding, Sea Islands brought UVD 4.2 and VCE 2.0, Volcanic Islands pushed to UVD 5.0 and 6.0 with VCE 3.0, and Arctic Islands reached UVD 6.3 with VCE 3.4. Vega added UVD 7.0 and VCE 4.0, while the Navi line transitioned to the VCN naming, progressing from VCN 2.0 on Navi 1X to VCN 5.0 on Navi 4X.

From 180 Nanometers to Modern Fab

The manufacturing progression across AMD/ATI's GPU lineup reflects the broader semiconductor industry's march toward smaller, denser transistors. The integrated graphics processors based on the Radeon VE (the 3xx IGP series) were fabricated at 180 nanometers, while the R200 generation moved to 150 nanometers. Each subsequent generation tightened the process node, allowing more transistors on a comparable die size and enabling richer core configurations. The core layout itself evolved: early chips described their pipeline in terms of pixel pipelines, vertex shaders, texture mapping units, and render output units, while later architectures shifted to unified shader models aligned with Direct3D 10 and beyond. Bus interfaces also migrated over time, with the R300 and R400 generations supporting both AGP 8× and PCIe ×16 variants, and later cards standardizing on PCIe. Specification tables track transistor counts, die surface area, core clock frequencies, fill rates, shader and vertex operation throughput, memory bus type and width, memory size and clock, theoretical bandwidth, and both TDP and TBP power figures—though the documentation cautions that these numbers should not be compared one-to-one across generations due to shifting conventions.

API Support and the Feature Gap

The rendering API support of each GPU generation defined what developers could build and what users could experience. The R100 series supported Direct3D 7.0 and OpenGL 1.3, a modest baseline for its era. The R200 generation stepped up to Direct3D 8.1 and OpenGL 1.4, while the R300 and R400 generations both reached Direct3D 9.0 (or 9.0b for R400) and OpenGL 2.0. A notable caveat appears in the X1000 series: despite being a later-generation product, these cards lacked Vertex Texture Fetch and therefore did not fully comply with the Vertex Shader 3.0 model, instead offering a partial feature set. The Rage series, the oldest in the lineup, provided only OpenGL 1.0 for generic 2D operations through software implementations rather than dedicated hardware. As architectures advanced, the distinction between pixel and vertex shaders gave way to unified shaders in Direct3D 10 and newer GPUs, fundamentally changing how shader operations were measured and how the pipeline was configured. API support tables across the full microarchitecture range document which rendering and computing APIs each generation's drivers enabled, though branding series could include chips from older generations, complicating a simple one-to-one mapping between product name and capability.