Computer hardware

Lore & Background

Some of the earliest computing devices date back to the seventeenth century. In 1642, French mathematician Blaise Pascal designed a gear-based device called the Pascaline that could add and subtract. In 1676, the stepped reckoner was invented by Gottfried Leibniz, which could also divide and multiply; due to limitations of contemporary fabrication and design flaws, it was not very functional, but similar devices remained in use into the 1970s. In the 19th century, Englishman Charles Babbage invented the difference engine, a mechanical device to calculate polynomials for astronomical purposes, and also designed a general-purpose computer that was never built. Much of that design was incorporated into the earliest computers: punch cards for input and output, memory, an arithmetic unit analogous to central processing units, and a primitive programming language similar to assembly language. In 1936, Alan Turing developed the concept of the universal Turing machine to model any type of computer, demonstrating that no machine could solve the decision problem. The universal Turing machine was a type of stored-program computer capable of mimicking the operations of any Turing machine based on the software instructions passed to it. In 1945, Turing finished the design for a computer (the Automatic Computing Engine) that was never built. Around this time, technological advancement in relays and vacuum tubes enabled the construction of the first computers. Building on Babbage's design, relay computers were built by George Stibitz at Bell Laboratories and Harvard University's Howard Aiken, who engineered the MARK I. Also in 1945, mathematician John von Neumann devised the underlying von Neumann architecture that has served as the template for most modern computers, featuring a centralized memory that stored both data and programs, a central processing unit (CPU) with priority of access to the memory, and input and output (I/O) units. Von Neumann used a single bus to transfer data, creating the Von Neumann bottleneck when the system tries to fetch both data and programs at the same time, often throttling the system's performance.

Reader's Guide

Computer architecture involves balancing various goals such as cost, speed, availability, and energy efficiency. The most common instruction set architecture (ISA) is based on the one devised by von Neumann in 1945. Common types of ISAs include CISC, RISC, vector operations, and hybrid modes. After the invention of RISC in the 1980s, RISC-based architectures that used pipelining and caching to increase performance displaced CISC architectures, particularly in applications with restrictions on power usage or space. From 1986 to 2003, the annual rate of improvement in hardware performance exceeded 50 percent, enabling the development of new computing devices such as tablets and mobiles. Alongside the density of transistors, DRAM memory as well as flash and magnetic disk storage also became exponentially more compact and cheaper. The rate of improvement slackened off in the twenty-first century. In the twenty-first century, increases in performance have been driven by increasing exploitation of parallelism, accommodated by various hardware strategies including instruction-level parallelism, vector architectures, graphical processing units (GPUs), thread-level parallelism, and request-level parallelism. Microarchitecture refers to high-level hardware questions such as the design of the CPU, memory, and memory interconnect. Memory hierarchy ensures that quicker-to-access memory is located closer to the CPU, while slower, cheaper memory for large-volume storage is located further away. Most computers use virtual memory to simplify addressing for programs. Cooling is critical: computer processors generate heat, and excessive heat impacts performance and can harm components. Many computer chips automatically throttle performance to avoid overheating. Computers typically have mechanisms for dissipating heat, such as air or liquid coolers for the CPU and GPU and heatsinks for other components. Power delivery and heat dissipation are the most challenging aspects of hardware design and have been the limiting factor to the development of smaller and faster chips since the early twenty-first century.

Did You Know?

• The Pascaline, designed in 1642 by Blaise Pascal, could only add and subtract.
• The von Neumann architecture, devised in 1945, uses a single bus to transfer data, creating the Von Neumann bottleneck.
• Most computers use virtual memory to simplify addressing for programs, with the operating system mapping virtual memory to different areas of finite physical memory.

From Gears to General Purpose: The Mechanical Dawn

Long before silicon chips or binary code, the dream of mechanical computation took shape through the ingenuity of European mathematicians. In 1642, Blaise Pascal crafted the Pascaline, a gear-driven machine capable of addition and subtraction. Three decades later, Gottfried Leibniz pushed further with his stepped reckoner, extending the capabilities to multiplication and division. Though plagued by fabrication limitations and design flaws that rendered it unreliable, the core mechanism—the Leibniz wheel—survived in practical use well into the 1970s. The nineteenth century brought Charles Babbage, who engineered the difference engine to compute polynomials for astronomical tables. More ambitiously, Babbage sketched a general-purpose computing machine that was never constructed in his lifetime. Yet his blueprint anticipated nearly every major component of modern hardware: punch cards for input and output, a dedicated memory store, an arithmetic unit functioning much like today's central processing unit, and even a rudimentary programming language resembling assembly. These mechanical forerunners laid the conceptual groundwork upon which every subsequent generation of computing hardware would be built.

Von Neumann and the Architecture That Endured

In 1945, while contributing to the ENIAC project at the University of Pennsylvania, mathematician John von Neumann articulated a design philosophy that would become the structural backbone of virtually every computer built since. His architecture placed a centralized memory at the heart of the system, storing both data and programs side by side. A central processing unit held priority access to that memory, while separate input and output units handled communication with the outside world. A single bus transferred data between these components. This elegant consolidation solved the storage problem of the era, but it also introduced a persistent constraint: when the system attempted to fetch both a program instruction and its data simultaneously through that one bus, performance throttled—a limitation now known as the Von Neumann bottleneck. The design had deeper intellectual roots. Alan Turing's 1936 universal Turing machine had already shown that a stored-program computer could mimic any other machine's operations based on the instructions fed to it, establishing the critical link between hardware and software that von Neumann's architecture made practical. And even earlier, George Boole's mid-nineteenth-century Boolean algebra—where every proposition resolves to true or false—provided the logical foundation for the transistor circuits inside today's integrated circuits.

The Instruction Set Wars: CISC, RISC, and the Mobile Revolution

The interface between a computer's hardware and its software is defined by its instruction set architecture, and the most common form traces directly to von Neumann's 1945 design. Two dominant philosophies emerged from this foundation. CISC, or complex instruction set computer, employs a broader expression set to minimize the total number of instructions a machine must execute. RISC, or reduced instruction set computer, takes the opposite approach, recognizing that only a handful of instructions are used frequently, and trims the set for simplicity while enabling more registers. The RISC revolution of the 1980s proved transformative. Coupled with pipelining and caching techniques, RISC-based architectures displaced CISC in many domains, especially where power and space were constrained, such as mobile phones. Between 1986 and 2003, annual hardware performance improvements exceeded fifty percent, a pace that made entirely new device categories—tablets, smartphones—feasible. During that same window, DRAM memory, flash storage, and magnetic disk drives all became exponentially more compact and cheaper. Manufacturers benefited from improved fabrication techniques that reduced component rejection at quality assurance, driving prices down even when raw performance plateaued. The result was a hardware landscape where cost, speed, and energy efficiency became the defining trade-offs for every designer.

Beyond the Single Core: The Parallelism Era

As the twenty-first century progressed, the rapid annual gains in hardware performance that had characterized the late twentieth century began to slow. The industry's answer was not faster single-threaded processing but a fundamental shift toward parallelism. Modern applications are typically parallelizable in two distinct ways: data parallelism, where the same function runs simultaneously across multiple chunks of data, and task parallelism, where different tasks execute concurrently with limited interaction between them. Hardware designers have responded with a layered toolkit. Instruction-level parallelism, exemplified by instruction pipelining, overlaps the execution of successive operations. Vector architectures process multiple data elements in a single operation. Graphical processing units, originally designed for rendering, proved exceptionally well suited to data parallelism and now handle a wide range of computational workloads. Thread-level and request-level parallelism add further dimensions, allowing multiple independent threads or network requests to be serviced simultaneously. Together, these strategies have become the primary engine of performance growth, replacing the earlier era of ever-faster clock speeds with ever-broader concurrency across the physical components of the machine.