Bitwise ternary logic instruction

Lore & Background

The bitwise ternary logic instruction has appeared in several instruction set architectures despite its unusual hardware cost. The 1985 Amiga blitter capability in Agnus implemented this operation as memory-to-memory, where the 8-bit immediate was termed 'minterm'. Later, the AVX-512 extension introduced it as vpternlog, and Power ISA v3.1 calls the instruction xxeval. Intel Larrabee also implemented this instruction as vpternlog; Tom Forsyth explains that Intel test engineers were happy to have one instruction to test rather than 256.

In mathematical terminology, each corresponding bit of the three inputs is a ternary Boolean function with a Hasse diagram of order n=8, also known as minterms. A full table showing all 256 possible 3-operand logical bitwise instructions may be found in the Power ISA description of xxeval. An additional insight is that if the 8-bit immediate were an operand (register), then in FPGA terminology, bitwise ternary logical instructions would implement an array of Hardware LUT3s.

The instruction works by using three single-bit inputs (r2, r1, r0) as a 3-bit index into the 8-bit immediate, returning the indexed bit. For 64-bit input registers, the output is correspondingly 64-bit, constructed by selecting each indexed bit of the three inputs to create the corresponding indexed bit of the output.

Reader's Guide

The bitwise ternary logic instruction is significant because it replaces up to 256 separate three-input Boolean operations with a single instruction, dramatically reducing code size and potentially increasing throughput. Its primary applications include bit manipulation for symmetric ciphers, as noted in the source article. Specific uses include carry-save operations, SHA-1, SHA-2, MD5, and exactly-one and exactly-two bitcounting used in Harley-Seal Popcount. The article states that vpternlog speeds up MD5 by 20%.

Despite its hardware cost, the instruction has been adopted in multiple architectures over decades, from the 1985 Amiga blitter to modern SIMD extensions like AVX-512 and Power ISA v3.1. Its legacy lies in providing a compact, flexible way to implement any three-input bitwise function, which is particularly valuable in cryptographic and bit-manipulation algorithms. The instruction's ability to implement an array of Hardware LUT3s in software also highlights its conceptual connection to FPGA design.

Did You Know?

• The 1985 Amiga blitter in Agnus implemented this instruction as memory-to-memory, calling the 8-bit immediate a 'minterm'.
• Intel test engineers were reportedly happy to have one instruction to test rather than 256, according to Tom Forsyth.
• The instruction can implement all 256 possible three-input bitwise operations using an 8-bit immediate as a lookup table.

Modular Design & Register Architecture

AVX-512 represents a fundamental expansion of Intel's x86 SIMD instruction set, extending the 256-bit Advanced Vector Extensions to operate on 512-bit registers. First proposed in mid-2013 and realized in the 2016 Knights Landing Xeon Phi, the instruction set broke with a long-standing design convention: rather than requiring implementers to adopt the entire block at once, AVX-512 is split into multiple independent extensions. Only the Foundation subset (AVX-512F) is mandatory across all implementations, while additional capabilities like conflict detection, exponential operations, and prefetching can be added selectively. A key architectural shift is the doubling of general-purpose vector registers from sixteen to thirty-two, alongside the introduction of eight dedicated mask registers. These opmask registers enable selective blending of instruction results, allowing programmers to control which elements of a vector are actually written back. This masking capability, combined with the wider register file, gives compilers and developers far greater flexibility in expressing parallel data transformations without resorting to manual element-wise workarounds.

Generational Rollout Across Processor Lines

The AVX-512 instruction set did not arrive all at once. Its extensions were introduced in waves tied to specific processor generations. The initial batch—Foundation, Conflict Detection, Exponential/Reciprocal, and Prefetch—debuted on Knights Landing and the Skylake-SP Purley platform, with the latter two being exclusive to the Xeon Phi line. Knights Mill then contributed deep-learning-focused extensions for variable-precision and single-precision fused multiply-accumulate operations. The Skylake-X and Cannon Lake generations brought the Vector Length extension, enabling 512-bit instructions to also target 128- and 256-bit registers, along with doubleword/quadword integer instructions and byte/word integer coverage. Cannon Lake further added integer fused multiply-add at 52-bit precision and vector bit-manipulation primitives. Cascade Lake introduced dedicated neural-network vector instructions, while Ice Lake layered on population-count, second-generation bit manipulation, bit-algorithm, and EVEX-encoded AES/GFNI/PCLMULQDQ variants. Tiger Lake added a vector pair-intersection instruction, and AMD's Zen 6 contributed a bit-matrix-multiply and bit-reversal extension. This staggered rollout reflects how different workloads drove different hardware priorities over time.

The EVEX Encoding Revolution

The existing VEX prefix that served AVX and AVX2 simply could not accommodate the feature set Intel envisioned for 512-bit operations. The solution was a new encoding scheme called EVEX, which restructured the instruction prefix to unlock several capabilities simultaneously. Most notably, EVEX expanded register addressing to cover all thirty-two 512-bit vector registers and incorporated the eight opmask registers directly into the encoding. It also introduced a scalar memory broadcast mode, where a single memory operand is automatically replicated across the full vector width, eliminating the need for explicit shuffle instructions. Per-instruction rounding control was embedded into the prefix, giving programmers fine-grained control over floating-point exception behavior without separate status-register manipulation. A compressed displacement addressing mode further reduced instruction size for common memory access patterns. Critically, the extended register file, the SIMD-width selector bit, and the opmask mechanism are all mandatory components that require operating-system support, making AVX-512 a deeper architectural commitment than its predecessors.

Predecessors, Successors & the Road Ahead

AVX-512 is not Intel's first foray into 512-bit SIMD. The first-generation Xeon Phi coprocessors, descended from the Larrabee project, already offered 512-bit vector instructions, but those were neither binary-compatible nor fully source-compatible with the later AVX-512 family. Looking forward, Intel announced AVX10 in July 2023 as the direct successor. AVX10 introduces a versioned model in which each successive revision subsumes all instructions from the prior one, simplifying runtime feature detection. In early specification drafts, 512-bit vector support was optional—potentially enabling E-core support—before Intel made it mandatory across both P-cores and E-cores. The first revision of AVX10 adds no new instructions beyond what AVX-512 already provides; for processors supporting 512-bit vectors, it is functionally equivalent to the subset found in Sapphire Rapids. Subsequent AVX10 versions are expected to introduce additional capabilities. Meanwhile, AMD and other vendors have joined the ecosystem, with Zen 6 contributing its own bit-manipulation extension, signaling that 512-bit SIMD has become a cross-vendor standard rather than an Intel-exclusive feature.