NEC V20

Lore & Background

The V20 was fabricated in 2-micron CMOS technology and had two 16-bit wide internal databuses, enabling two data transfers to occur concurrently. Early versions ran at 5, 8, and 10 MHz; later versions added 12 and 16 MHz. In 1990, an upgrade to the fabrication process produced the V20H and V20HL, with improved performance and reduced power consumption. The V20HLs were completely static, allowing their clock to be stopped. The V20 was reported to be compatible with the Intel 8087 floating-point unit coprocessor. NEC designed its own FPU, the μPD72091, which was cancelled before reaching production, followed by the μPD72191, though it is unclear how many, if any, of that second part were produced. The V30, a nearly identical CPU with a 16-bit external data bus, debuted on September 1, 1983.

Reader's Guide

The V20's significance lies in its legal and technical challenges to Intel's dominance. Intel sued NEC in 1982 over the μPD8086 and μPD8088, settling out of court with a licensing agreement. In late 1984, Intel again sued, claiming the V20 and V30 microcode infringed its patents. The court ruled on September 22, 1986, that microcode in a control store is a computer program protected by copyright, but found Intel had forfeited its copyright by neglecting to ensure second-source chips were marked. The court also determined NEC did not copy Intel's microcode and that the V20 and V30 microcode was sufficiently different to not infringe. The judge accepted NEC's cleanroom evidence and approved its use of reverse engineering for the Rev.2 microcode. The V20's ISA extensions included bit manipulation, packed BCD operations, and new real-mode instructions from the Intel 80286. It also offered a mode to emulate an Intel 8080 CPU, entered via a BRKEM instruction and exited with RETEM, with a CALLN instruction to mix x86 code. Another mode put the processor into a power-saving state via a HALT instruction.

Did You Know?

• The V20 could emulate an Intel 8080 CPU via a BRKEM instruction.
• NEC designed two FPU coprocessors for the V20, the μPD72091 (cancelled) and the μPD72191 (production unclear).
• The V20 had instructions to extract and insert bit fields of arbitrary lengths (EXT, INS).

Architecture and Performance

The NEC V20, introduced in November 1982, was built around a die containing 63,000 transistors—more than double the 29,000 found in the Intel 8088 it was designed to replace. That transistor budget enabled two internal 16-bit databuses that could move data simultaneously, a structural advantage that let the chip retire more instructions per clock than an 8088 running at the same frequency. NEC also targeted a 50 percent clock duty cycle, a significant departure from the 33 percent figure Intel had used. Fabricated in 2-micron CMOS, early V20 parts ran at 5, 8, and 10 MHz. By 1990, a process upgrade yielded the V20H and V20HL variants, which delivered better performance at lower power draw, and later revisions pushed speeds to 12 and 16 MHz. The V20HLs were fully static designs, meaning the clock could be halted entirely when the processor was idle. Externally, the chip presented an 8-bit data bus multiplexed onto the lower address pins and a 20-bit address line capable of reaching one megabyte of memory, while internally it operated as a 16-bit machine.

Instruction Set Extensions

Beyond its 8088-compatible core, the V20 carried a suite of instructions that Intel's own 8088 could not execute. Packed BCD arithmetic was handled by ADD4S, SUB4S, and CMP4S, which operated on large multi-byte decimal numbers stored directly in memory. Nibble-level rotation was available through ROL4 and ROR4. A family of single-bit operations—TEST1, SET1, CLR1, and NOT1—let programmers inspect, set, clear, or flip individual bits, though these were notably less efficient than the BT, BTS, BTR, and BTC instructions that would later appear in the i80386, and their encodings were not compatible. Two further instructions, EXT and INS, extracted and inserted bit fields of arbitrary length. The string-scan loop was extended with REPC and REPNC prefixes, which modified the behavior of SCAS and CMPS based on a less-than or not-less-than condition. Perhaps most strikingly, the V20 could enter a full Intel 8080 emulation mode via a BRKEM instruction, exit it with RETEM, and even mix native x86 calls into 8080 code through a CALLN instruction. A HALT instruction placed the chip into a low-power state.

The Intel Litigation

NEC's path to releasing the V20 was shadowed by two separate legal confrontations with Intel. The first, filed in 1982, targeted NEC's earlier μPD8086 and μPD8088 clones; it was settled out of court, with NEC agreeing to license the designs directly from Intel. The second suit, brought in late 1984, alleged that the microcode inside the V20 and its sibling V30 infringed Intel's patents on the 8088 and 8086. NEC software engineer Hiroaki Kaneko had studied both the hardware architecture and the original Intel microcode during the design process. On September 22, 1986, the court ruled that microcode stored in a control store qualifies as a computer program and is therefore eligible for copyright protection. However, the judge found that Intel had forfeited its copyright by failing to properly mark all second-source chips. Critically, the court also concluded that NEC had not simply copied Intel's microcode; the V20 and V30 code was sufficiently distinct to avoid infringement. The judge accepted NEC's cleanroom development evidence and approved the use of reverse engineering in producing the Rev.2 microcode.

Ecosystem and Successors

The V20 did not exist in isolation. In September 1983, NEC shipped the V30, a nearly identical processor that widened the external data bus to 16 bits, making it pin- and object-code compatible with the Intel 8086 rather than the 8088. On the coprocessor front, the V20 was reported to work with Intel's 8087 floating-point unit. NEC also attempted to design its own FPU, the μPD72091, but that project was cancelled before it reached production. A revised design, the μPD72191, followed, though it remains unclear whether any units were actually manufactured. The V20's ISA, which shared similarities with the Intel 80188 while adding its own extensions, influenced later thinking about alternate instruction set modes. NEC's broader x86-compatibility strategy also produced the μPD9002, a CPU that combined Z80 and x86 compatibility, and the RX116, a dedicated 16-bit RTOS processor based on ITRON-1. The V20's approach of embedding an alternate instruction set within a mainstream architecture found a conceptual echo in VIA Technologies' Alternate Instruction Set scheme.