National Semiconductor PACE

Lore & Background

The PACE was a single-chip version of National Semiconductor's IMP-16, a five-chip set from early 1973 that was inspired by the Data General Nova minicomputer. To the basic IMP-16, PACE added a new operational mode called "byte mode" for working with 8-bit data such as ASCII text. Implemented in pMOS, as was common for the era, the PACE required three supply voltages and an external clock with enough signal to drive the internal logic, normally supplied by the System Timing Element (STE) chip. Most PACE systems also required the Bidirectional Transceiver Element (BTE) to convert the higher internal voltage signals to TTL levels used by the rest of the system. Its multiplexed address and data pins required additional logic to latch the address between cycles.

The PACE had ten 16-bit internal locations that held the topmost stack values. A unique feature was that when the stack was almost full and another push was attempted, or it was empty after a pull, an interrupt was generated, allowing interrupt handler code to copy values to or from main memory. The Status and Control Flag register was 16 bits wide, with bits including CRY (carry), OVF (overflow), LINK (for shift/rotate operations), IN EN (interrupt enable), and the BYTE flag for 8-bit data access. Bits 1 through 5 were interrupt enable flags (IE1–IE5) used for priority interrupt control, while bits F11 through F14 provided direct control outputs for external devices.

All instructions were 16 bits wide. The top six bits held the opcode, bits 8 and 9 indicated addressing mode (Relative and indeX), and the remaining eight bits normally held an address. Addressing modes included direct base page, PC-relative, and indexed using AC2 or AC3. Indirect addressing was supported primarily by the LD and ST instructions using separate opcodes. The base page could be split between the first and last 128 bytes when the BPS pin was asserted, allowing external devices to be mapped onto high memory.

Reader's Guide

The PACE holds historical significance as the first commercial single-chip 16-bit microprocessor, marking a transition from multi-chip CPU implementations to single-chip designs. Its architecture, derived from the Data General Nova minicomputer, brought minicomputer-like capabilities to a single chip. The addition of byte mode addressed the need for 8-bit data handling, particularly for ASCII text. However, the PACE's pMOS implementation required three supply voltages and external support chips (STE and BTE), complicating system design. Its multiplexed address/data pins and non-TTL voltage levels added further complexity. National Semiconductor had second source agreements with Signetics and Rockwell, but neither produced the design. The PACE was followed by the INS8900, implemented in nMOS, which fixed several bugs, simplified electrical interfacing, and increased speed by about 50%. By the time the INS8900 was available, higher-performance 16-bit CPUs were appearing, and National Semiconductor began to deemphasize sales of the line.

Did You Know?

• The PACE was the first commercial single-chip 16-bit microprocessor, announced in late 1974.
• It added a 'byte mode' for working with 8-bit data like ASCII text, which was not present in the IMP-16.
• The PACE had ten internal 16-bit stack locations that could generate an interrupt when nearly full or empty, acting as a cache for a larger memory-based stack.
• The Status and Control Flag register included separate CRY and LINK flags, allowing carry and shift/rotate bits to be tracked separately.

Core Architecture and Operational Logic

A microprocessor is, at its heart, a clock-driven, register-based digital circuit that lives on a single integrated circuit or a small handful of them. It houses the full complement of arithmetic, logic, and control hardware that a central processing unit requires, and it is capable of reading machine code, interpreting it, and carrying out arithmetic operations. Its input and output are both binary, and it processes data according to instructions stored in memory. Internally, the chip blends combinational logic with sequential digital logic to manipulate numbers and symbols in the binary system. The arithmetic logic unit handles addition, subtraction, and bitwise operations like AND and OR, while a control logic section pulls opcodes from memory and orchestrates the sequence of internal operations needed to complete each instruction. A single opcode can ripple across many data paths and registers. After each operation, flags in a status register record outcomes such as zero results, negative values, or overflow conditions.

The Integration Revolution and Its Economic Consequences

Before the microprocessor era, small computers were assembled from racks of circuit boards populated with numerous medium- and small-scale integrated circuits, typically of the TTL variety. The arrival of very-large-scale integration changed everything by collapsing an entire CPU onto one or a few large-scale ICs. Because these chips are manufactured in enormous volumes through highly automated metal-oxide-semiconductor fabrication processes, the unit price stays remarkably low. Consolidating logic onto fewer chips also improves reliability, since there are fewer electrical connections that can develop faults. Rock's law observes that as designs grow more sophisticated on a chip of the same physical size, manufacturing cost generally remains flat. The cumulative effect has been dramatic: other forms of computing hardware have become nearly obsolete, and one or more microprocessors now appear in everything from the tiniest embedded controllers to the most powerful supercomputers. The first commercially available microprocessor, the Intel 4004 designed by Federico Faggin and introduced in 1971, marks the starting point of this transformation, though credit for the invention remains debated.

Scaling Complexity and the Memory Hierarchy

The physical boundaries of an integrated circuit—how many transistors fit on the die, how many package pins can reach outside, how many internal interconnections are possible, and how much heat the chip can shed—set a ceiling on processor complexity. As fabrication technology advances, that ceiling rises, and the consequences are visible in the processor's architecture. Word sizes have grown from four and eight bits to the sixty-four-bit words of modern designs. More transistors on a single die have allowed additional on-chip registers to accelerate program execution and enabled complex instruction sets that produce more compact code. Floating-point arithmetic, which early eight-bit processors could only emulate in software, first appeared as a separate integrated circuit and later migrated onto the same chip as the core processor, dramatically speeding up numerical work. Perhaps most critically, the ability to place large transistor counts on one die made it practical to integrate memory directly alongside the processor. This on-die cache offers faster access than off-chip memory and has become essential because processor clock frequencies have outpaced the speed of external memory, meaning the CPU would otherwise stall waiting for data.

Specialized Derivatives and the Power-Performance Trade-off

While the microprocessor is a general-purpose engine, several specialized processing devices have branched off from its lineage. Digital signal processors are architected specifically for signal-processing workloads, graphics processing units target real-time image rendering, and microcontrollers serve embedded systems and peripheral devices. Systems on a chip frequently combine one or more processor cores with radio modems and other components, powering smartphones and tablets. Hardware accelerators offload particular functions away from the general-purpose core. Choosing among these options involves a fundamental trade-off tied to word size. A longer word lets each clock cycle perform more computation, but it demands a physically larger die and higher standby and operating power. Four-, eight-, and twelve-bit processors remain common in low-power embedded microcontrollers, while sixteen-, thirty-two-, and sixty-four-bit designs handle larger data volumes and more flexible interfaces. In mixed-signal applications containing noise-sensitive analog components like high-resolution converters, an eight- or sixteen-bit processor may be preferred over a thirty-two-bit one to preserve signal integrity, and emulating thirty-two-bit arithmetic on an eight-bit chip can paradoxically consume more power than a native thirty-two-bit design.