Microprocessors, Part 2 Codexery

Ignite (microprocessor)

A two-stack RISC microprocessor for embedded and virtual machine execution.

Ignite (microprocessor)

The Ignite (stylized as IGNITE, and formerly called ShBoom and PSC 1000) is a microprocessor architecture that uses a two-stack, stack machine design, falling under the reduced instruction set computer (RISC) category. Developed by Russell H. Fish III and Chuck H. Moore at Nanotronics—later acquired by Patriot Scientific Corporation—it stands as one of the few commercially available processors built around a stack-based computing model. Its intended uses were primarily embedded systems, thanks to its low power consumption, and efficient execution of virtual stack machines, including the Java virtual machine and the stack machine behind the Forth programming language. The product did not succeed commercially.

Among its notable features, the Ignite operates internally at a speed faster than its external clock. Each instruction fetch can read up to four instructions, which lowers memory-bandwidth demands compared to typical 32-bit RISC processors. This trait also enables looping over a group of instructions—a micro-loop—without needing additional instruction fetches from memory. It supports single-cycle subroutine calls (plus memory access) and implicit subroutine returns. The processor can interpret Java at near-native speed without a just-in-time compiler, using roughly 20 kilobytes of code. It also offers low-power operation.

Quick Facts

Designer
Nanotronics, PTSC
Bits
32-bit
Design
RISC
Endianness
Big
Gpr
52 (including stacks)

Facts from the source article.

Lore & Background

The Ignite architecture was originally developed by Russell H. Fish III and Chuck H. Moore at Nanotronics, which was later acquired by Patriot Scientific Corporation. The processor's unusual two-stack design set it apart from conventional register-based RISC architectures. It was one of the few commercially produced microprocessors to adopt a stack-based computing model, aiming to efficiently execute stack-oriented languages and virtual machines.

Notable features include the ability to run faster than the clock internally, and the capability to read up to four instructions on each instruction fetch, reducing memory-bandwidth requirements compared to typical 32-bit RISC machines. This characteristic also allowed looping on an instruction group (a micro-loop) without additional instruction fetches from memory. The processor offered single-cycle (plus memory) subroutine calls and implicit subroutine returns. It could achieve near-native speed Java interpretation with no JIT required, in approximately 20K bytes of code, and operated with low power consumption.

The product was unsuccessful in the market.

Reader's Guide

The Ignite microprocessor's significance lies in its demonstration of a commercially viable stack-based RISC architecture, a rarity among microprocessors. Its design specifically targeted low-power embedded devices and efficient execution of stack-based virtual machines, such as the Java virtual machine and the Forth programming language. The ability to run faster than the internal clock and fetch up to four instructions per cycle reduced memory bandwidth demands, while micro-looping eliminated repeated instruction fetches. The processor's implicit subroutine return and single-cycle subroutine call further streamlined execution. Despite these technical innovations, the Ignite did not achieve market success. Its legacy remains as an example of an alternative computing model that prioritized stack operations and virtual machine efficiency over the dominant register-based paradigm, and as a product of the collaboration between Russell H. Fish III and Chuck H. Moore, the latter known for his work on the Forth language.

Did You Know?

More in Microprocessors, Part 2 1-24

Spotted an error? Know more?

Reader corrections go straight into our review queue. Suggest an edit · How this site is sourced

Comments

Loading…
Open in the interactive codex →