EnCore Processor

The EnCore processor family is a configurable, extensible 32-bit RISC microprocessor design developed by the PASTA Research Group at the University of Edinburgh School of Informatics. It uses a compact instruction set architecture that supports freely mixed 16-bit and 32-bit encodings for high code density, with no overhead when switching between them. The processor features a five-stage pipeline, claims the highest operating frequency in its class, and achieves very low dynamic energy consumption—99% of its flip-flops are automatically clock-gated by standard synthesis tools. Most non-memory operations complete in a single cycle, and there is at most one load-delay slot. Cache architectures are easily configurable.

All EnCore test chips are named after hills in Edinburgh. The first, Calton, is the smallest. The second, Castle, is named after the rock on which Edinburgh Castle sits.

**EnCore Calton** Calton is the first silicon implementation of the EnCore processor, fabricated in a generic 130nm CMOS process using a standard ASIC flow. It implements the baseline configuration extended with a barrel shifter, multiplier, and a full set of 32 general-purpose registers. The chip includes bus interface and system control functions alongside the processor core, with 8KB direct-mapped instruction and data caches. The complete system-on-chip occupies 1 mm² of silicon at 75% utilization. Chip-level power consumption is 25 mW at 250 MHz, and first silicon samples operate above 375 MHz at typical voltage and temperature.

**EnCore Castle** Castle is the second silicon implementation of an extended EnCore processor, fabricated in a generic 90nm CMOS process. It contains an extended processor core with a 32KB 4-way set-associative instruction cache and a 32KB 4-way set-associative data cache, embedded in a system-on-chip that provides a generic 32-bit memory interface, interrupts, clocks, and reset signals. The design uses generic free foundry libraries and a stack of nine metal layers. The complete design occupies 2.25 mm² on a 1.875 × 1.875 mm die, including the baseline CPU, reconfigurable Configurable Flow Accelerator (CFA) extension logic, two 32KB caches, and off-chip interfaces. It operates on a core voltage of 0.9V to 1.1V with 2.5V LVCMOS I/O signals, and is packaged in a 68-pin Ceramic LCC.