CVAX
DEC's second-generation single-chip VAX microprocessor chipset.
The CVAX chipset, created by Digital Equipment Corporation (DEC), implemented the VAX instruction set architecture. It included the CVAX 78034 central processing unit, the CFPA floating-point accelerator, a clock chip, and several support chips: the CVAX System Support Chip (CSSC), the CVAX Memory Controller (CMCTL), and the CVAX Q-Bus Interface Chip (CQBIC). Systems using this chipset first shipped in late 1987.
The CVAX 78034, also called the MicroVAX 78034, was a second-generation single-chip VAX microprocessor. It ran at 12.5 MHz (80 ns) in higher-end systems like the VAX 6000 Model 200, and at 11.11 MHz (90 ns) in lower-end systems such as the MicroVAX 3500 and 3600. It was the first VAX microprocessor with an internal cache—a combined 1 KB instruction and data stream cache. Unusually, this cache used one-transistor DRAM cells instead of the typical SRAM, chosen to reduce the cache array’s area; the designers estimated that using four-transistor DRAM or six-transistor SRAM would have required 2.4 to 3 times more space. The internal cache occupied a narrow strip along the left side of the die, and an external 64 KB cache supplemented it.
The 78034 contained 134,000 transistors on a 9.7 by 7.4 mm (71.78 mm²) die, fabricated in DEC’s first-generation CMOS-1 process (2.0 μm, two layers of aluminum interconnect). It came in an 84-pin ceramic chip carrier with a heat sink, used a single +5 V power supply, and dissipated up to 1.5 W. The microprocessor was microprogrammed and partially pipelined, with six major functional units: the I-Box, E-Box, M-Box, bus interface unit (BIU), cache, and control store with microsequencer. The I-Box fetched VAX instructions from the cache and decoded them into macroinstructions using an instruction decode ROM (IROM). The E-Box contained a register file (31 single-read-port/single-write-port registers and eight dual-read-port/single-write-port registers), a 32-bit program counter, a constant generator, a shifter, and a 32-bit ALU capable of addition, subtraction, and logic operations. A dedicated shifter handled most shifting, while a less powerful shifter in the ALU executed integer multiply and divide instructions. The register file’s design allowed more simultaneous register access for higher performance. The M-Box served as the memory management unit, with a 28-entry fully associative translation look-aside buffer (TLB)
- Manufacturer
- Digital Equipment Corporation (DEC)
- Introduced
- Late 1987
- Clock speed
- 12.5 MHz (80 ns) in higher-end systems; 11.11 MHz (90 ns) in lower-end systems
- Transistor count
- 134,000 (CVAX 78034); 65,000 (CFPA)
- Process
- CMOS-1, 2.0 μm, two layers of aluminium interconnect
- Die size
- 9.7 × 7.4 mm (71.78 mm²) for 78034; 7.3 × 9.1 mm (66.43 mm²) for CFPA
- Power dissipation
- Maximum 1.5 W (78034)
Lore & Background
The CVAX chipset's central component, the CVAX 78034, was the first VAX microprocessor to include an internal cache, a 1 KB combined instruction and data stream cache. This cache was unusual because it was implemented with one-transistor DRAM cells rather than the SRAM typical of most microprocessors; DEC chose DRAM to reduce the cache array's area, as four-transistor DRAM or six-transistor SRAM cells would have required 2.4 to 3 times more area. The internal cache occupied a narrow strip along the left side of the die, and an external 64 KB cache complemented it.
The 78034 was microprogrammed and partially pipelined, containing six major functional units: the I-Box (instruction fetch and decode), E-Box (execution unit with register file, ALU, shifter), M-Box (memory management unit with a 28-entry fully associative TLB), bus interface unit (BIU), cache, and control store with microsequencer. The control store held 1,600 41-bit words of microcode. The CFPA floating-point coprocessor contained 65,000 transistors and was packaged in a 68-pin surface-mountable chip carrier.
A shrunk version, CVAX+, was fabricated in DEC's CMOS-2 1.5 μm process; the shrunk 78034 (CVAX-60) taped out in August 1987, before the original 78034 began volume production, and the CFPA-60 taped out in November 1987. CVAX+ operated at 16.67 MHz with unchanged power requirements and began shipping in late 1988 as upgrades to entry-level CVAX systems and to the VAX 6000 when Rigel's introduction was delayed by yield issues.
Reader's Guide
The CVAX chipset represented a significant step in DEC's strategy to bring the VAX architecture to smaller, lower-cost systems. By integrating the CPU onto a single chip and using a DRAM-based internal cache to save die area, DEC achieved a compact design that could be clocked at 12.5 MHz in higher-end systems like the VAX 6000 Model 200 and at 11.11 MHz in lower-end systems such as the MicroVAX 3500 and 3600. The chipset's modularity—with separate CPU, floating-point accelerator, clock chip, and support chips—allowed DEC to configure systems for different performance and cost points.
The CVAX+ optical shrink, fabricated in a smaller 1.5 μm process, extended the chipset's life by boosting clock speed to 16.67 MHz without increasing power dissipation, and it served as a stopgap upgrade when the next-generation Rigel faced yield problems. The later SOC (system-on-chip) variant integrated the CPU, FPU, clock chip, and an 8 KB second-level cache on a single die, operating at 25 or 28.5 MHz, and was used in entry-level servers, workstations, X terminals, and as an embedded processor in DEC's printers and terminals. The CVAX family thus bridged the gap between earlier multi-chip VAX implementations and later highly integrated microprocessors, demonstrating DEC's ability to adapt its proprietary architecture to evolving semiconductor technology.
Did You Know?
- The CVAX 78034 was the first microprocessor to use one-transistor DRAM for its internal cache.
- The internal cache was only 1 KB, but an external 64 KB cache complemented it.
- The CVAX+ optical shrink taped out before the original CVAX began volume production.
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